Hi,here is the POST output by the serial console....
======================================================
coreboot-4.0-r Mon Apr 12 13:20:12 CST 2010 starting... now booting... real_main Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... Core0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 freq_cap1=0x35, freq_cap2=0x75 dev1 old_freq=0x0, freq=0x5, needs_reset=0x1 dev2 old_freq=0x0, freq=0x5, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 01K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 0101Xht reset - soft reset
coreboot-4.0-r Mon Apr 12 13:20:12 CST 2010 starting... now booting... real_main Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... Core0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 freq_cap1=0x35, freq_cap2=0x75 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change
Rudolf Marek wrote:
00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change
No other messages after this? What was wrong last time?
No more messages,but if I comment the fid/vid related code out(maybe due to my Sempron 3000 lack of CnQ??),every thing looks fine except the coreboot does not excute payload(SeaBIOS) correctly....
does coreboot excute payload or not?
On Thu, Apr 15, 2010 at 12:15 AM, Chi Min Wang cmwang@ms1.hinet.net wrote:
Rudolf Marek wrote:
00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT
freq: 05 VIA HT caps: 0075 00after enable_fid_change
No other messages after this? What was wrong last time?
No more messages,but if I comment the fid/vid related code out(maybe due
to my Sempron 3000 lack of CnQ??),every thing looks fine except the coreboot does not excute payload(SeaBIOS) correctly....
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Qing Pei Wang wrote:
does coreboot excute payload or not?
Coreboot says no vaild CBFS header found....BTW,with Sempron 3400(which support CnQ),coreboot could create ACPI_PSS object correctly,so the fid/vid related code should check if the CPU is CnQ capable(although it should be rarely needed for current situation)....
following for attachment log, there is no payload was found actually. I think there is on payload within coreboot.bin. is there a payload.elf in the coreboot/trunk/ directory?
On Thu, Apr 15, 2010 at 4:17 PM, Chi Min Wang cmwang@ms1.hinet.net wrote:
Qing Pei Wang wrote:
does coreboot excute payload or not?
Coreboot says no vaild CBFS header found....BTW,with Sempron 3400(which
support CnQ),coreboot could create ACPI_PSS object correctly,so the fid/vid related code should check if the CPU is CnQ capable(although it should be rarely needed for current situation)....
Qing Pei Wang wrote:
following for attachment log, there is no payload was found actually. I think there is on payload within coreboot.bin. is there a payload.elf in the coreboot/trunk/ directory?
but I could see folowing message while make the image,and even "cbfstool coreboot.rom print" shows there is payload in the image....
CBFS coreboot.rom PAYLOAD bios.bin.elf-0.6.0 (compression: LZMA) VGABIOS vgabios.bin 1106,3230 CBFSPRINT coreboot.romcoreboot.rom: 512 kB, bootblocksize 674, romsize 524288, offset 0x0 Alignment: 64 bytes
Name Offset Type Size fallback/romstage 0x0 stage 45921 fallback/coreboot_ram 0xb3c0 stage 50082 fallback/payload 0x177c0 payload 40443 pci1106,3230.rom 0x21600 optionrom 39424 (empty) 0x2b040 null 347350
-
Chi Min Wang -
Qing Pei Wang -
Rudolf Marek