New patch to review for coreboot: 4ed0d36 Add sb800 spi support. It is for S3, storing the recovring data in the nonvolatile storage, i.e., flash.
Zheng Bao (zheng.bao@amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/620
-gerrit
commit 4ed0d36ae46fa37b7ea9d5dcc68d0e4d0e4f5e7e Author: zbao zheng.bao@amd.com Date: Mon Feb 13 16:21:34 2012 +0800
Add sb800 spi support. It is for S3, storing the recovring data in the nonvolatile storage, i.e., flash.
Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9 Signed-off-by: Zheng Bao zheng.bao@amd.com --- src/southbridge/amd/cimx/sb800/Makefile.inc | 2 + src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 4 + src/southbridge/amd/cimx/sb800/spi.c | 210 +++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/spi.h | 42 ++++++ 4 files changed, 258 insertions(+), 0 deletions(-)
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 30d2133..2b55fee 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -27,6 +27,8 @@ romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c
+ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c + driver-y += smbus.c driver-y += lpc.c
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index db5343d..25aba95 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -158,4 +158,8 @@ typedef union _PCI_ADDR {
#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
+#if CONFIG_HAVE_ACPI_RESUME == 1 +#include "spi.h" +#endif + #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c new file mode 100644 index 0000000..ed8f51d --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -0,0 +1,210 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include "SBPLATFORM.h" + + +void executeCommand(volatile u8 * spi_address) +{ + *(spi_address + 2) |= 1; +} + +void wait4CommandComplete(volatile u8 * spi_address) +{ + while (*(spi_address + 2) & 1) + printk(BIOS_DEBUG, "wait4CommandComplete\n"); +} + +void resetInternalFIFOPointer(volatile u8 * spi_address) +{ + u8 val; + + do { + *(spi_address + 2) |= 0x10; + val = *(spi_address + 0xd); + } while (val & 0x7); +} + +u8 readSPIStatus(volatile u8 * spi_address) +{ + u8 val; + *spi_address = 0x05; + *(spi_address + 1) = 0x11; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = 0x0; /* dummy */ + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + resetInternalFIFOPointer(spi_address); + val = *(spi_address + 0xC); + val = *(spi_address + 0xC); + return val; +} + +void wait4FlashPartReady(volatile u8 * spi_address) +{ + while (readSPIStatus(spi_address) & 1) ; +} + +void writeSPIStatus(volatile u8 * spi_address, u8 status) +{ + *spi_address = 0x50; /* EWSR */ + *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ + executeCommand(spi_address); + wait4CommandComplete(spi_address); + + *spi_address = 0x01; /* WRSR */ + *(spi_address + 1) = 0x01; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = status; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); + + readSPIStatus(spi_address); +} + +void readSPIID(volatile u8 * spi_address) +{ + u8 mid = 0, did = 0; + *spi_address = 0x90; + *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = 0; + *(spi_address + 0xC) = 0; + *(spi_address + 0xC) = 0; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + resetInternalFIFOPointer(spi_address); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + + mid = *(spi_address + 0xC); + did = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); +} + +void SPIWriteEnable(volatile u8 * spi_address) +{ + *spi_address = 0x06; /* Write Enable */ + *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ + executeCommand(spi_address); + wait4CommandComplete(spi_address); + //wait4FlashPartReady(spi_address); +} + +void sectorEraseSPI(volatile u8 * spi_address, u32 address) +{ + SPIWriteEnable(spi_address); + *spi_address = 0x20; + *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ + + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void chipEraseSPI(volatile u8 * spi_address) +{ + SPIWriteEnable(spi_address); + *spi_address = 0xC7; + *(spi_address + 1) = 0x00; + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void byteProgram(volatile u8 * spi_address, u32 address, u32 data) +{ + SPIWriteEnable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 4; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void dwordnoneAAIProgram(volatile u8 * spi_address, u32 address, u32 data) +{ + u8 i; + /* + * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); + */ + for (i = 0; i < 4; i++) { + SPIWriteEnable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 4; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + data >>= 8; + address++; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); + } +} + +void dwordProgram(volatile u8 * spi_address, u32 address, u32 data) +{ + SPIWriteEnable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 7; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + *(spi_address + 0xC) = (data >> 8) & 0xFF; + *(spi_address + 0xC) = (data >> 16) & 0xFF; + *(spi_address + 0xC) = (data >> 24) & 0xFF; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void directByteProgram(volatile u8 * spi_address, volatile u32 * address, u32 data) +{ + SPIWriteEnable(spi_address); + *address = data; + wait4FlashPartReady(spi_address); +} diff --git a/src/southbridge/amd/cimx/sb800/spi.h b/src/southbridge/amd/cimx/sb800/spi.h new file mode 100644 index 0000000..1e781f8 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/spi.h @@ -0,0 +1,42 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _SB800_CIMX_SPI_H_ +#define _SB800_CIMX_SPI_H_ + +void executeCommand(volatile u8 * spi_address); +void wait4CommandComplete(volatile u8 * spi_address); +void resetInternalFIFOPointer(volatile u8 * spi_address); +u8 readSPIStatus(volatile u8 * spi_address); +void wait4FlashPartReady(volatile u8 * spi_address); +void writeSPIStatus(volatile u8 * spi_address, u8 status); +void readSPIID(volatile u8 * spi_address); +void SPIWriteEnable(volatile u8 * spi_address); +void sectorEraseSPI(volatile u8 * spi_address, u32 address); +void chipEraseSPI(volatile u8 * spi_address); +void byteProgram(volatile u8 * spi_address, u32 address, u32 data); +void dwordnoneAAIProgram(volatile u8 * spi_address, u32 address, u32 data); +void dwordProgram(volatile u8 * spi_address, u32 address, u32 data); +void directByteProgram(volatile u8 * spi_address, volatile u32 * address, u32 data); + +#endif
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Zheng Bao