Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

[Keith Hui]

Hi all,

This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other
related changes (below), so it is gzipped. I may have committed a few
"crimes" here, but anyway...

First, I found out why the debug output isn't correct - A typo caused
the cache size to got lost amid the shuffle. It has been fixed in this
version.

This patch:
1. Brings back L2 initialization from coreboot v1 for family 63x,65x
and 67x CPUs. Need someone with a Mendocino Celeron to see if the
entire 128k of L2 is still enabled.
2. Split model_67x/65x and model_63x from model_6xx. model_67x also
serves model 65x because they share too much code. Also included are
Intel microcode for all CPUs in these families. There's just one file
for all microcodes in one family.
3. In Slot 1 Makefile.inc, conditionally bring in sources in models
63x/67x/6bx only when the proper config has been selected in Kconfig.
Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has
been selected.
4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the
mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above.
5. Blocked out some apparently unused #includes from model_6xx_init.c.
Once we're sure nothing really are using it, then remove them.

Bootlog with a PIII 600MHz can be found here:
http://coreboot.pastebin.com/PNUzJXZT

Have fun, bon appetit and cheers.

Signed-off-by: Keith Hui

On Wed, May 12, 2010 at 12:16 PM, Joseph Smith  wrote:
> On Wed, 12 May 2010 11:48:57 -0400, Keith Hui  wrote:
> > Yes, the debug output from the L2 init code does say 128K, but
> > /proc/cpuinfo reports 512K. This is where I'd like some expert
> > opinions.
>
> Sure, but we need to see the code to give an opinion :-)

[PATCH] SECC Pentium 2/3 users are gonna love this

[Joseph Smith]

On 05/13/2010 10:03 PM, Keith Hui wrote:
> Hi all,
>
> This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other
> related changes (below), so it is gzipped. I may have committed a few
> "crimes" here, but anyway...
>
> First, I found out why the debug output isn't correct - A typo caused
> the cache size to got lost amid the shuffle. It has been fixed in this
> version.
>
> This patch:
> Brings back L2 initialization from coreboot v1 for family 63x,65x
>
> and 67x CPUs. Need someone with a Mendocino Celeron to see if the
> entire 128k of L2 is still enabled.
> 2. Split model_67x/65x and model_63x from model_6xx. model_67x also
> serves model 65x because they share too much code. Also included are
> Intel microcode for all CPUs in these families. There's just one file
> for all microcodes in one family.
> 3. In Slot 1 Makefile.inc, conditionally bring in sources in models
> 63x/67x/6bx only when the proper config has been selected in Kconfig.
> Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has
> been selected.
> 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the
> mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above.
> 5. Blocked out some apparently unused #includes from model_6xx_init.c.
> Once we're sure nothing really are using it, then remove them.
>
> Bootlog with a PIII 600MHz can be found here:
> http://coreboot.pastebin.com/PNUzJXZT
>
> Have fun, bon appetit and cheers.
>
> Signed-off-by: Keith Hui

This looks awesome Keith! Great Work :-)
I can only see one thing that needs fixing and it is cosmetic:

Lines 394-395 of bootlog look good:

CPU: vendor Intel device 673
CPU: family 06, model 07, stepping 03

But, Line 411 of bootlog:  CPU: .

+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);

Is the %s not working?

Otherwise,
Acked-by: Joseph Smith

[PATCH] SECC Pentium 2/3 users are gonna love this

[Keith Hui]

On Thu, May 13, 2010 at 10:28 PM, Joseph Smith  wrote:
> On 05/13/2010 10:03 PM, Keith Hui wrote:
> > Hi all,
> >
> > This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other
> > related changes (below), so it is gzipped. I may have committed a few
> > "crimes" here, but anyway...
> >
> > First, I found out why the debug output isn't correct - A typo caused
> > the cache size to got lost amid the shuffle. It has been fixed in this
> > version.
> >
> > This patch:
> > Brings back L2 initialization from coreboot v1 for family 63x,65x
> >
> > and 67x CPUs. Need someone with a Mendocino Celeron to see if the
> > entire 128k of L2 is still enabled.
> > 2. Split model_67x/65x and model_63x from model_6xx. model_67x also
> > serves model 65x because they share too much code. Also included are
> > Intel microcode for all CPUs in these families. There's just one file
> > for all microcodes in one family.
> > 3. In Slot 1 Makefile.inc, conditionally bring in sources in models
> > 63x/67x/6bx only when the proper config has been selected in Kconfig.
> > Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has
> > been selected.
> > 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the
> > mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above.
> > 5. Blocked out some apparently unused #includes from model_6xx_init.c.
> > Once we're sure nothing really are using it, then remove them.
> >
> > Bootlog with a PIII 600MHz can be found here:
> > http://coreboot.pastebin.com/PNUzJXZT
> >
> > Have fun, bon appetit and cheers.
> >
> > Signed-off-by: Keith Hui
>
> This looks awesome Keith! Great Work :-)
> I can only see one thing that needs fixing and it is cosmetic:
>
> Lines 394-395 of bootlog look good:
>
> CPU: vendor Intel device 673
> CPU: family 06, model 07, stepping 03
>
> But, Line 411 of bootlog:  CPU: .
> /* Print processor name */
> fill_processor_name(processor_name);
> printk(BIOS_INFO, "CPU: %s.\n", processor_name);
>
> Is the %s not working?

I think that's because Katmai doesn't support processor brand string
through CPUID. See page 3-197, volume 2A, Intel Software Developer's
Manual

It's cosmetic. This code can be removed from model 63x and 67x in the
next patch.

Thanks
Keith

[PATCH] SECC Pentium 2/3 users are gonna love this

[Keith Hui]

The original patch was unclean as pork (didn't apply cleanly). Please
use this one instead.

Thanks Joseph.

And edit your board's romstage similar to patch below:

Index: src/mainboard/asus/p2b-ls/romstage.c
===================================================================
--- src/mainboard/asus/p2b-ls/romstage.c	(revision 5543)
+++ src/mainboard/asus/p2b-ls/romstage.c	(working copy)
@@ -33,7 +33,9 @@
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
+#if CONFIG_ROMCC==1
 #include "cpu/x86/mtrr/earlymtrr.c"
+#endif
 #include "cpu/x86/bist.h"
 /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
@@ -46,12 +48,20 @@
 }

#include "northbridge/intel/i440bx/raminit.c"
+#if CONFIG_DEBUG_RAM_SETUP
 #include "northbridge/intel/i440bx/debug.c"
+#endif

-static void main(unsigned long bist)
+#if CONFIG_ROMCC
+static /* This is part of main() declaration below for romcc only. */
+#endif
+
+void main(unsigned long bist)
 {
+#if CONFIG_ROMCC
    if (bist == 0)
    	early_mtrr_init();
+#endif

/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
    w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -63,10 +73,14 @@
    i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */

enable_smbus();
-	/* dump_spd_registers(); */
+#if CONFIG_DEBUG_RAM_SETUP
+	dump_spd_registers();
+#endif	
    sdram_set_registers();
    sdram_set_spd_registers();
    sdram_enable();
-	/* ram_check(0, 640 * 1024); */
+#if CONFIG_DEBUG_RAM_SETUP
+	ram_check(0, 640 * 1024);
+#endif
 }
> This patch:
> Brings back L2 initialization from coreboot v1 for family 63x,65x
>
> and 67x CPUs. Need someone with a Mendocino Celeron to see if the
> entire 128k of L2 is still enabled.
> 2. Split model_67x/65x and model_63x from model_6xx. model_67x also
> serves model 65x because they share too much code. Also included are
> Intel microcode for all CPUs in these families. There's just one file
> for all microcodes in one family.
> 3. In Slot 1 Makefile.inc, conditionally bring in sources in models
> 63x/67x/6bx only when the proper config has been selected in Kconfig.
> Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has
> been selected.
> 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the
> mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above.
> 5. Blocked out some apparently unused #includes from model_6xx_init.c.
> Once we're sure nothing really are using it, then remove them.
>
> Bootlog with a PIII 600MHz can be found here:
> http://coreboot.pastebin.com/PNUzJXZT
>
> Have fun, bon appetit and cheers.

Signed-off-by: Keith Hui

[PATCH] SECC Pentium 2/3 users are gonna love this

[Idwer Vollering]

2010/5/14 Keith Hui
> The original patch was unclean as pork (didn't apply cleanly). Please
> use this one instead.
>
> Thanks Joseph.
>
> And edit your board's romstage similar to patch below:
> Index: src/mainboard/asus/p2b-ls/romstage.c
>
> --- src/mainboard/asus/p2b-ls/romstage.c        (revision 5543)
> +++ src/mainboard/asus/p2b-ls/romstage.c        (working copy)
> @@ -33,7 +33,9 @@
>  #include "lib/debug.c"
>  #include "pc80/udelay_io.c"
>  #include "lib/delay.c"
> +#if CONFIG_ROMCC==1
>  #include "cpu/x86/mtrr/earlymtrr.c"
> +#endif
>  #include "cpu/x86/bist.h"
>  /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
>  #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
> @@ -46,12 +48,20 @@
>  }
>
> #include "northbridge/intel/i440bx/raminit.c"
> +#if CONFIG_DEBUG_RAM_SETUP
>  #include "northbridge/intel/i440bx/debug.c"
> +#endif
>
> -static void main(unsigned long bist)
> +#if CONFIG_ROMCC
> +static /* This is part of main() declaration below for romcc only. */
> +#endif
>
> +void main(unsigned long bist)
>  {
> +#if CONFIG_ROMCC
>        if (bist == 0)
>                early_mtrr_init();
> +#endif
>    /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
>    w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
>
> @@ -63,10 +73,14 @@
>        i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
>    enable_smbus();
>   /* dump_spd_registers(); */
>
> +#if CONFIG_DEBUG_RAM_SETUP
>   dump_spd_registers();
>
> +#endif
>        sdram_set_registers();
>        sdram_set_spd_registers();
>        sdram_enable();
>   /* ram_check(0, 640 * 1024); */
>
> +#if CONFIG_DEBUG_RAM_SETUP
>   ram_check(0, 640 * 1024);
>
> +#endif
>  }

The only additional adjustment I had to make was in raminit.c:

Index: src/northbridge/intel/i440bx/raminit.c
===================================================================
--- src/northbridge/intel/i440bx/raminit.c      (revision 5543)
+++ src/northbridge/intel/i440bx/raminit.c      (working copy)
@@ -947,7 +947,7 @@
        set_dram_row_attributes();

/* TODO: Set SDRAMC. */
-       pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config
*/
+       pci_write_config16(NB, SDRAMC, 0x0000); /* SDRAMPWR=0: 3 DIMM config
*/

/* TODO */
        set_dram_buffer_strength();
> > This patch:
> > Brings back L2 initialization from coreboot v1 for family 63x,65x
> >
> > and 67x CPUs. Need someone with a Mendocino Celeron to see if the
> > entire 128k of L2 is still enabled.
> > 2. Split model_67x/65x and model_63x from model_6xx. model_67x also
> > serves model 65x because they share too much code. Also included are
> > Intel microcode for all CPUs in these families. There's just one file
> > for all microcodes in one family.
> > 3. In Slot 1 Makefile.inc, conditionally bring in sources in models
> > 63x/67x/6bx only when the proper config has been selected in Kconfig.
> > Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has
> > been selected.
> > 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the
> > mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above.
> > 5. Blocked out some apparently unused #includes from model_6xx_init.c.
> > Once we're sure nothing really are using it, then remove them.
> >
> > Bootlog with a PIII 600MHz can be found here:
> > http://coreboot.pastebin.com/PNUzJXZT

Bootlog with a 450MHz P3: http://coreboot.pastebin.com/DAqztY9H

[    0.005829] CPU: L1 I cache: 16K, L1 D cache: 16K
[    0.005952] CPU: L2 cache: 512K
> > Have fun, bon appetit and cheers.
>
> Signed-off-by: Keith Hui

[PATCH] SECC Pentium 2/3 users are gonna love this

[Keith Hui]

On Fri, May 14, 2010 at 10:10 AM, Idwer Vollering  wrote:
> 2010/5/14 Keith Hui
> > The original patch was unclean as pork (didn't apply cleanly). Please
> > use this one instead.
> >
> > Thanks Joseph.
> >
> > And edit your board's romstage similar to patch below:
>
> The only additional adjustment I had to make was in raminit.c:
> Index: src/northbridge/intel/i440bx/raminit.c
>
> --- src/northbridge/intel/i440bx/raminit.c      (revision 5543)
> +++ src/northbridge/intel/i440bx/raminit.c      (working copy)
> @@ -947,7 +947,7 @@
>         set_dram_row_attributes();
>
> /* TODO: Set SDRAMC. */
> -       pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config
> */
> +       pci_write_config16(NB, SDRAMC, 0x0000); /* SDRAMPWR=0: 3 DIMM config
> */
>
> /* TODO */
>         set_dram_buffer_strength();

So the reason you were having your problems seems to be your CPUID
isn't included in the family_67x whitelist of CPUIDs. No compiled in
CPU driver claims your cpuid, then it just dies.

Hmm... You have the same cpuid as mine. Interesting.

Anyway, That line you edited should have been removed altogether as
that register was already set elsewhere. I submitted a cleanup patch
for this and don't know how it end up. BTW enable CAR and try again.
We want to officially migrate the ASUS P2B family to CAR.

Cheers
Keith

[PATCH] SECC Pentium 2/3 users are gonna love this

[Idwer Vollering]

2010/5/14 Keith Hui

BTW enable CAR and try again.

Like this (note that it doesn't boot my asus p2b, rev 1.04):

svn diff src/mainboard/asus/p2b/Kconfig
Index: src/mainboard/asus/p2b/Kconfig
===================================================================
--- src/mainboard/asus/p2b/Kconfig      (revision 5543)
+++ src/mainboard/asus/p2b/Kconfig      (working copy)
@@ -25,7 +25,9 @@
        select NORTHBRIDGE_INTEL_I440BX
        select SOUTHBRIDGE_INTEL_I82371EB
        select SUPERIO_WINBOND_W83977TF
-       select ROMCC
+#      select ROMCC
+       select USE_PRINTK_IN_CAR
+       select CONFIG_USE_DCACHE_RAM
        select HAVE_PIRQ_TABLE
        select UDELAY_TSC
        select BOARD_ROMSIZE_KB_256
@@ -50,3 +52,13 @@
        default 6
        depends on BOARD_ASUS_P2B

+config DCACHE_RAM_BASE
+       hex
+       default 0xffdf8000
+       depends on BOARD_ASUS_P2B
+
+config DCACHE_RAM_SIZE
+       hex
+       default 0x8000
+       depends on BOARD_ASUS_P2B
+

[PATCH] SECC Pentium 2/3 users are gonna love this

[Keith Hui]

Limit your DCACHE_RAM_SIZE to 0x1000 (4k). The L2 init is done
post-raminit so it's not available for CAR. Your CPU only has 16k of
L1 cache available for CAR.

HTH
Keith

On Fri, May 14, 2010 at 12:51 PM, Idwer Vollering  wrote:
> 2010/5/14 Keith Hui
> > BTW enable CAR and try again.
>
> Like this (note that it doesn't boot my asus p2b, rev 1.04):
>
> svn diff src/mainboard/asus/p2b/Kconfig
> Index: src/mainboard/asus/p2b/Kconfig
> ===================================================================
> --- src/mainboard/asus/p2b/Kconfig      (revision 5543)
> +++ src/mainboard/asus/p2b/Kconfig      (working copy)
> @@ -25,7 +25,9 @@
>         select NORTHBRIDGE_INTEL_I440BX
>         select SOUTHBRIDGE_INTEL_I82371EB
>         select SUPERIO_WINBOND_W83977TF
> -       select ROMCC
> +#      select ROMCC
> +       select USE_PRINTK_IN_CAR
> +       select CONFIG_USE_DCACHE_RAM
>         select HAVE_PIRQ_TABLE
>         select UDELAY_TSC
>         select BOARD_ROMSIZE_KB_256
> @@ -50,3 +52,13 @@
>         default 6
>         depends on BOARD_ASUS_P2B
>
> +config DCACHE_RAM_BASE
> +       hex
> +       default 0xffdf8000
> +       depends on BOARD_ASUS_P2B
>
> +config DCACHE_RAM_SIZE
> +       hex
> +       default 0x8000
> +       depends on BOARD_ASUS_P2B

[PATCH] SECC Pentium 2/3 users are gonna love this

[Idwer Vollering]

2010/5/14 Keith Hui
> Limit your DCACHE_RAM_SIZE to 0x1000 (4k). The L2 init is done
> post-raminit so it's not available for CAR. Your CPU only has 16k of
> L1 cache available for CAR.

Bootlog+dmesg :)

coreboot-4.0-r5543M Fri May 14 20:31:05 CEST 2010 starting...
SMBus controller enabled

dimm: 00.0: 50
00: 80 08 04 0c 0a 01 40 00 01 80 60 00 80 08 00 01
10: 8f 04 06 01 01 00 0e a0 60 00 00 14 14 14 32 20
20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 f6
40: 7f da 00 00 00 00 00 00 53 44 50 31 30 30 2d 30
50: 36 34 31 36 32 45 00 00 00 00 00 00 00 01 45 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 af
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dimm: 01.0: 51
00: 80 08 04 0c 09 01 40 00 01 80 60 00 80 08 00 01
10: 8f 04 06 01 01 00 0e 0c 60 00 00 14 10 14 30 10
20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 ff
40: da 43 4d 45 4d 4f 52 59 53 50 44 50 31 30 30 2d
50: 30 36 34 30 38 33 41 55 00 00 00 00 00 98 50 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ad
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dimm: 02.0: 52
00: 80 08 04 0c 09 01 40 00 01 75 54 00 80 08 00 01
10: 8f 04 06 01 01 00 0f a0 60 00 00 14 0f 14 2d 10
20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 8f
40: 7f 94 ff ff ff ff ff ff 04 47 4d 4d 32 36 34 39
50: 32 33 33 45 54 47 2d 37 35 20 20 00 ff 22 64 88
60: f2 d0 2d 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ad
80: 43 50 51 31 15 38 30 34 38 46 52 34 5a 30 42 50
90: 37 20 01 14 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
dimm: 03.0: 53
00: bad device

Northbridge prior to SDRAM init:
Found DIMM in slot 00
Found DIMM in slot 01
Found DIMM in slot 02
PGPOL[BPR] has been set to 0x15
RPS has been set to 0x0112
NBXECC[31:24] has been set to 0xff
DRAMC has been set to 0x08
RAM Enable 1: Apply NOP
RAM Enable 2: Precharge all
RAM Enable 3: CBR
RAM Enable 4: Mode register set
RAM Enable 5: Normal operation
RAM Enable 6: Enable refresh
    Enabling refresh (DRAMC = 0x09) for DIMM 00
    Enabling refresh (DRAMC = 0x09) for DIMM 01
    Enabling refresh (DRAMC = 0x09) for DIMM 02
Northbridge following SDRAM init:
Testing DRAM : 00000000 - 000a0000
DRAM fill: 0x00000000-0x000a0000
000a0000
DRAM filled
DRAM verify: 0x00000000-0x000a0000
000a0000
DRAM range verified.
Done.
Loading stage image.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (212992 bytes), entry @
0x100000
Stage: done loading.
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-4.0-r5543M Fri May 14 20:31:05 CEST 2010 booting...
POST: 0x40
Calibrating delay loop...
end 922a0e65, start 5f8a0bcf
32-bit delta 810
calibrate_tsc 32-bit result is 810
clocks_per_usec: 810
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:04.0: enabled 1, 0 resources
PNP: 03f0.0: enabled 1, 3 resources
PNP: 03f0.1: enabled 1, 2 resources
PNP: 03f0.2: enabled 1, 2 resources
PNP: 03f0.3: enabled 1, 2 resources
PNP: 03f0.5: enabled 1, 4 resources
PNP: 03f0.7: enabled 1, 0 resources
PNP: 03f0.8: enabled 1, 0 resources
PNP: 03f0.9: enabled 1, 0 resources
PNP: 03f0.a: enabled 1, 0 resources
PCI: 00:04.1: enabled 1, 0 resources
PCI: 00:04.2: enabled 1, 0 resources
PCI: 00:04.3: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:00.0: enabled 1, 0 resources
  PCI: 00:01.0: enabled 1, 0 resources
  PCI: 00:04.0: enabled 1, 0 resources
   PNP: 03f0.0: enabled 1, 3 resources
   PNP: 03f0.1: enabled 1, 2 resources
   PNP: 03f0.2: enabled 1, 2 resources
   PNP: 03f0.3: enabled 1, 2 resources
   PNP: 03f0.5: enabled 1, 4 resources
   PNP: 03f0.7: enabled 1, 0 resources
   PNP: 03f0.8: enabled 1, 0 resources
   PNP: 03f0.9: enabled 1, 0 resources
   PNP: 03f0.a: enabled 1, 0 resources
  PCI: 00:04.1: enabled 1, 0 resources
  PCI: 00:04.2: enabled 1, 0 resources
  PCI: 00:04.3: enabled 1, 0 resources
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
Finding PCI configuration type.
PCI: Using configuration type 1
POST: 0x5f
PCI_DOMAIN: 0000 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:00.0 [8086/7190] ops
PCI: 00:00.0 [8086/7190] enabled
PCI: 00:01.0 [8086/7191] enabled
PCI: 00:04.0 [8086/7110] bus ops
PCI: 00:04.0 [8086/7110] enabled
PCI: 00:04.1 [8086/7111] ops
PCI: 00:04.1 [8086/7111] enabled
PCI: 00:04.2 [8086/7112] ops
PCI: 00:04.2 [8086/7112] enabled
PCI: 00:04.3 [8086/7113] bus ops
PCI: 00:04.3 [8086/7113] enabled
POST: 0x25
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
POST: 0x24
POST: 0x25
PCI: pci_scan_bus returning with max=001
POST: 0x55
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:04.0
malloc Enter, size 1092, free_mem_ptr 00130000
malloc 00130000
PNP: 03f0.0 enabled
PNP: 03f0.1 enabled
PNP: 03f0.2 enabled
PNP: 03f0.3 enabled
PNP: 03f0.5 enabled
PNP: 03f0.7 enabled
PNP: 03f0.8 enabled
PNP: 03f0.9 enabled
PNP: 03f0.a enabled
PNP: 03f0.6 enabled
scan_static_bus for PCI: 00:04.0 done
scan_static_bus for PCI: 00:04.3
scan_static_bus for PCI: 00:04.3 done
PCI: pci_scan_bus returning with max=001
POST: 0x55
scan_static_bus for Root Device done
done
POST: 0x66
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:04.0 read_resources bus 0 link: 0
PNP: 03f0.8 missing read_resources
PNP: 03f0.9 missing read_resources
PCI: 00:04.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device links 1 child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
   APIC: 00 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags
40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff
flags 40040200 index 10000100
   PCI: 00:00.0 links 0 child on link 0 NULL
   PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit
ffffffff flags 1200 index 10
   PCI: 00:01.0 links 1 child on link 0 NULL
   PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags
80102 index 1c
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
81202 index 24
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
80202 index 20
   PCI: 00:04.0 links 1 child on link 0 PNP: 03f0.0
   PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags
c0000100 index 1
   PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0
flags c0000200 index 2
   PCI: 00:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3
    PNP: 03f0.0 links 0 child on link 0 NULL
    PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
    PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800
index 74
    PNP: 03f0.1 links 0 child on link 0 NULL
    PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
    PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74
    PNP: 03f0.2 links 0 child on link 0 NULL
    PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
    PNP: 03f0.3 links 0 child on link 0 NULL
    PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
    PNP: 03f0.5 links 0 child on link 0 NULL
    PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
c0000100 index 60
    PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags
c0000100 index 62
    PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400
index 70
    PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400
index 72
    PNP: 03f0.7 links 0 child on link 0 NULL
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags
100 index 60
    PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100
index 62
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 03f0.8 links 0 child on link 0 NULL
    PNP: 03f0.9 links 0 child on link 0 NULL
    PNP: 03f0.a links 0 child on link 0 NULL
    PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 03f0.6 links 0 child on link 0 NULL
    PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100
index 60
    PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
   PCI: 00:04.1 links 0 child on link 0 NULL
   PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100
index 20
   PCI: 00:04.2 links 0 child on link 0 NULL
   PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100
index 20
   PCI: 00:04.3 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0
limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
ffff done
PCI: 00:04.2 20 *  [0x0 - 0x1f] io
PCI: 00:04.1 20 *  [0x20 - 0x2f] io
PCI_DOMAIN: 0000 compute_resources_io: base: 30 size: 30 align: 5 gran: 0
limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0
limit: ffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done
PCI: 00:00.0 10 *  [0x0 - 0xfffffff] prefmem
PCI_DOMAIN: 0000 compute_resources_mem: base: 10000000 size: 10000000 align:
28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:04.0
constrain_resources: PNP: 03f0.0
constrain_resources: PNP: 03f0.1
constrain_resources: PNP: 03f0.2
constrain_resources: PNP: 03f0.3
constrain_resources: PNP: 03f0.5
constrain_resources: PNP: 03f0.7
constrain_resources: PNP: 03f0.8
constrain_resources: PNP: 03f0.9
constrain_resources: PNP: 03f0.a
constrain_resources: PNP: 03f0.6
constrain_resources: PCI: 00:04.1
constrain_resources: PCI: 00:04.2
constrain_resources: PCI: 00:04.3
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
        lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff
        lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:30 align:5 gran:0
limit:ffff
Assigned: PCI: 00:04.2 20 *  [0x1000 - 0x101f] io
Assigned: PCI: 00:04.1 20 *  [0x1020 - 0x102f] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1030 size: 30 align: 5
gran: 0 done
PCI: 00:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12
limit:ffff
PCI: 00:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran:
12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10000000
align:28 gran:0 limit:febfffff
Assigned: PCI: 00:00.0 10 *  [0xe0000000 - 0xefffffff] prefmem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0000000 size: 10000000
align: 28 gran: 0 done
PCI: 00:01.0 allocate_resources_prefmem: base:febfffff size:0 align:20
gran:20 limit:febfffff
PCI: 00:01.0 allocate_resources_prefmem: next_base: febfffff size: 0 align:
20 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20
limit:febfffff
PCI: 00:01.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20
gran: 20 done
Root Device assign_resources, bus 0 link: 0
Setting RAM size to 256 MB
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c
prefmem
PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c
bus 01 io
PCI: 00:01.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14
bus 01 prefmem
PCI: 00:01.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14
bus 01 mem
PCI: 00:04.0 assign_resources, bus 0 link: 0
PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00
irq
PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00
drq
PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io
PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00
irq
ERROR: PNP: 03f0.1 74 drq size: 0x0000000001 not assigned
PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00
irq
PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00
irq
PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00
irq
PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00
irq
ERROR: PNP: 03f0.7 60 io size: 0x0000000001 not assigned
ERROR: PNP: 03f0.7 62 io size: 0x0000000002 not assigned
ERROR: PNP: 03f0.7 70 irq size: 0x0000000001 not assigned
ERROR: PNP: 03f0.a 70 irq size: 0x0000000001 not assigned
ERROR: PNP: 03f0.6 60 io size: 0x0000000008 not assigned
ERROR: PNP: 03f0.6 70 irq size: 0x0000000001 not assigned
PCI: 00:04.0 assign_resources, bus 0 link: 0
PCI: 00:04.1 20 <- [0x0000001020 - 0x000000102f] size 0x00000010 gran 0x04
io
PCI: 00:04.2 20 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05
io
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device links 1 child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00
   APIC: 00 links 0 child on link 0 NULL
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 1000 size 30 align 5 gran 0 limit ffff
flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 28 gran 0
limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index a
  PCI_DOMAIN: 0000 resource base c0000 size ff40000 align 0 gran 0 limit 0
flags e0004200 index b
   PCI: 00:00.0 links 0 child on link 0 NULL
   PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit
febfffff flags 60001200 index 10
   PCI: 00:01.0 links 1 child on link 0 NULL
   PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags
60080102 index 1c
   PCI: 00:01.0 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60081202 index 24
   PCI: 00:01.0 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60080202 index 20
   PCI: 00:04.0 links 1 child on link 0 PNP: 03f0.0
   PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags
c0000100 index 1
   PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0
flags c0000200 index 2
   PCI: 00:04.0 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3
    PNP: 03f0.0 links 0 child on link 0 NULL
    PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
    PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400
index 70
    PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800
index 74
    PNP: 03f0.1 links 0 child on link 0 NULL
    PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
    PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400
index 70
    PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74
    PNP: 03f0.2 links 0 child on link 0 NULL
    PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
    PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400
index 70
    PNP: 03f0.3 links 0 child on link 0 NULL
    PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
    PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400
index 70
    PNP: 03f0.5 links 0 child on link 0 NULL
    PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
e0000100 index 60
    PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags
e0000100 index 62
    PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400
index 70
    PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400
index 72
    PNP: 03f0.7 links 0 child on link 0 NULL
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags
100 index 60
    PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100
index 62
    PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 03f0.8 links 0 child on link 0 NULL
    PNP: 03f0.9 links 0 child on link 0 NULL
    PNP: 03f0.a links 0 child on link 0 NULL
    PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 03f0.6 links 0 child on link 0 NULL
    PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100
index 60
    PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
   PCI: 00:04.1 links 0 child on link 0 NULL
   PCI: 00:04.1 resource base 1020 size 10 align 4 gran 4 limit ffff flags
60000100 index 20
   PCI: 00:04.2 links 0 child on link 0 NULL
   PCI: 00:04.2 resource base 1000 size 20 align 5 gran 5 limit ffff flags
60000100 index 20
   PCI: 00:04.3 links 0 child on link 0 NULL
Done allocating resources.
POST: 0x88
Enabling resources...
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 0083
PCI: 00:01.0 cmd <- 00
PCI: 00:04.0 cmd <- 07
PCI: 00:04.1 cmd <- 01
PCI: 00:04.2 cmd <- 01
PCI: 00:04.3 cmd <- 01
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00009000, offset=0x00100000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor Intel device 673
CPU: family 06, model 07, stepping 03
microcode_info: sig = 0x00000673 pf=0x00000001 rev = 0x00000000
microcode updated to revision: 0000000e from revision 00000000
Configuring L2 cache... rdmsr(IA32_PLATFORM_ID) = 0, 11010000
L2 Cache latency is 8
Sending 0 to set_l2_register4
L2 ECC Checking is enabled
L2 Physical Address Range is 4096M
Maximum cache mask is 20000
L2 Cache Mask is 4000
read_l2(2) = 8
write_l2(2) = 8
L2 Cache size is 512K
L2 Cache lines initialized
done.
POST: 0x60
Enabling cache
CPU: .

Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Setting variable MTRR 0, base:    0MB, range:  256MB, type WB
ADDRESS_MASK_HIGH=0xf
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
POST: 0x6a

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
Setting up local apic... apic_id: 0x00 done.
POST: 0x9b
CPU #0 initialized
All AP CPUs stopped
PCI: 00:00.0 init
Northbridge Init
PCI: 00:04.0 init
RTC Init
PNP: 03f0.0 init
PNP: 03f0.1 init
PNP: 03f0.2 init
PNP: 03f0.3 init
PNP: 03f0.5 init
Keyboard init...
No PS/2 keyboard detected.
PNP: 03f0.7 init
PNP: 03f0.a init
PCI: 00:04.1 init
IDE: Primary IDE interface: on
IDE: Secondary IDE interface: on
IDE: Access to legacy IDE ports: on
IDE: Primary IDE interface, drive 0: UDMA/33: off
IDE: Primary IDE interface, drive 1: UDMA/33: off
IDE: Secondary IDE interface, drive 0: UDMA/33: off
IDE: Secondary IDE interface, drive 1: UDMA/33: off
PCI: 00:04.2 init
PNP: 03f0.6 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 4 resources
PCI: 00:00.0: enabled 1, 1 resources
PCI: 00:01.0: enabled 1, 3 resources
PCI: 00:04.0: enabled 1, 3 resources
PNP: 03f0.0: enabled 1, 3 resources
PNP: 03f0.1: enabled 1, 3 resources
PNP: 03f0.2: enabled 1, 2 resources
PNP: 03f0.3: enabled 1, 2 resources
PNP: 03f0.5: enabled 1, 4 resources
PNP: 03f0.7: enabled 1, 3 resources
PNP: 03f0.8: enabled 1, 0 resources
PNP: 03f0.9: enabled 1, 0 resources
PNP: 03f0.a: enabled 1, 1 resources
PCI: 00:04.1: enabled 1, 1 resources
PCI: 00:04.2: enabled 1, 1 resources
PCI: 00:04.3: enabled 1, 0 resources
PNP: 03f0.6: enabled 1, 2 resources
POST: 0x89
Initializing CBMEM area to 0xfff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 0fff0200...ok
High Tables Base is fff0000.
POST: 0x9a
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x0fff0400... done.
PIRQ table: 128 bytes.
POST: 0x9d
Multiboot Information structure has been written.
POST: 0x9d
Adding CBMEM entry as no. 3
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum dbdf
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x0fff1400
rom_table_end = 0x0fff1400
Adjust low_table_end from 0x00000518 to 0x00001000
Adjust rom_table_end from 0x0fff1400 to 0x10000000
Adding high table area
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000000ffeffff: RAM
 3. 000000000fff0000-000000000fffffff: CONFIGURATION TABLES
Wrote coreboot table at: 0fff1400 - 0fff159c  checksum 357a
coreboot table: 412 bytes.
POST: 0x9e
 0. FREE SPACE 0fff3400 0000cc00
 1. GDT        0fff0200 00000200
 2. IRQ TABLE  0fff0400 00001000
 3. COREBOOT   0fff1400 00002000
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
CBFS: follow chain: fffc0000 + 38 + f81a + align -> fffcf880
Check fallback/payload
Got a payload
Loading segment from rom address 0xfffcf8b8
  data (compression=1)
malloc Enter, size 36, free_mem_ptr 00130444
malloc 00130444
  New segment dstaddr 0xec200 memsize 0x13e00 srcaddr 0xfffcf8f0 filesize
0x9e22
  (cleaned up) New segment addr 0xec200 size 0x13e00 offset 0xfffcf8f0
filesize 0x9e22
Loading segment from rom address 0xfffcf8d4
  Entry Point 0x000fdfb7
Loading Segment: addr: 0x00000000000ec200 memsz: 0x0000000000013e00 filesz:
0x0000000000009e22
lb: [0x0000000000100000, 0x0000000000134000)
Post relocation: addr: 0x00000000000ec200 memsz: 0x0000000000013e00 filesz:
0x0000000000009e22
using LZMA
[ 0x00000000000ec200, 0000000000100000, 0x0000000000100000) <-
00000000fffcf8f0
dest 000ec200, end 00100000, bouncebuffer ff88000
Loaded segments
Jumping to boot code at fdfb7
POST: 0xfe
entry    = 0x000fdfb7
lb_start = 0x00100000
lb_size  = 0x00034000
adjust   = 0x0febc000
buffer   = 0x0ff88000
     elf_boot_notes = 0x0011ecdc
adjusted_boot_notes = 0x0ffdacdc
Start bios (version 0.6.0-20100428_024716-asus-p2b)
Found mainboard ASUS P2B
Found CBFS header at 0xfffeffe0
Ram Size=0x0fff0000 (0x0000000000000000 high)
CPU Mhz=451
Found 1 cpu(s) max supported 1 cpu(s)
Copying PIR from 0x0fff0400 to 0x000f7b30
SMBIOS ptr=0x000f7b10 table=0x0ffefef0
Scan for VGA option rom
UHCI init on dev 00:04.2 (io=1000)
Found 1 lpt ports
Found 2 serial ports
ATA controller 0 at 1f0/3f4/0 (irq 14 dev 21)
ATA controller 1 at 170/374/0 (irq 15 dev 21)
ata1-0: MAXTOR 6L060J3 ATA-5 Hard-Disk (57259 MiBytes)
drive 0x000f7a90: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
s=117266688
ebda moved from 9f400 to 9f000
USB keyboard initialized
Got ps2 nak (status=51)
Scan for option roms
Press F12 for boot menu.

Returned 53248 bytes of ZoneHigh
e820 map has 5 items:
  0: 0000000000000000 - 000000000009f000 = 1
  1: 000000000009f000 - 00000000000a0000 = 2
  2: 00000000000f0000 - 0000000000100000 = 2
  3: 0000000000100000 - 000000000ffed000 = 1
  4: 000000000ffed000 - 0000000010000000 = 2
enter handle_19:
  NULL
Booting from Floppy...
Boot failed: could not read the boot disk

enter handle_18:
  NULL
Booting from CD-Rom...
Boot failed: Could not read from CDROM (code 0001)
enter handle_18:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00
pnp call arg1=0
pnp call arg1=5

$ dmesg
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 2.6.32-22-generic (buildd@rothera) (gcc version
4.4.3 (Ubuntu 4.4.3-4ubuntu5) ) #33-Ubuntu SMP Wed Apr 28 13:27:30 UTC 2010
(Ubuntu 2.6.32-22.33-generic 2.6.32.11+drm33.2)
[    0.000000] KERNEL supported cpus:
[    0.000000]   Intel GenuineIntel
[    0.000000]   AMD AuthenticAMD
[    0.000000]   NSC Geode by NSC
[    0.000000]   Cyrix CyrixInstead
[    0.000000]   Centaur CentaurHauls
[    0.000000]   Transmeta GenuineTMx86
[    0.000000]   Transmeta TransmetaCPU
[    0.000000]   UMC UMC UMC UMC
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009f000 (usable)
[    0.000000]  BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved)
[    0.000000]  BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
[    0.000000]  BIOS-e820: 0000000000100000 - 000000000ffed000 (usable)
[    0.000000]  BIOS-e820: 000000000ffed000 - 0000000010000000 (reserved)
[    0.000000] DMI 2.4 present.
[    0.000000] last_pfn = 0xffed max_arch_pfn = 0x100000
[    0.000000] MTRR default type: uncachable
[    0.000000] MTRR fixed ranges enabled:
[    0.000000]   00000-9FFFF write-back
[    0.000000]   A0000-BFFFF uncachable
[    0.000000]   C0000-FFFFF write-back
[    0.000000] MTRR variable ranges enabled:
[    0.000000]   0 base 000000000 mask FF0000000 write-back
[    0.000000]   1 disabled
[    0.000000]   2 disabled
[    0.000000]   3 disabled
[    0.000000]   4 disabled
[    0.000000]   5 disabled
[    0.000000]   6 disabled
[    0.000000]   7 disabled
[    0.000000] PAT not supported by CPU.
[    0.000000] e820 update range: 0000000000002000 - 0000000000006000
(usable) ==> (reserved)
[    0.000000] Scanning 1 areas for low memory corruption
[    0.000000] modified physical RAM map:
[    0.000000]  modified: 0000000000000000 - 0000000000002000 (usable)
[    0.000000]  modified: 0000000000002000 - 0000000000006000 (reserved)
[    0.000000]  modified: 0000000000006000 - 000000000009f000 (usable)
[    0.000000]  modified: 000000000009f000 - 00000000000a0000 (reserved)
[    0.000000]  modified: 00000000000f0000 - 0000000000100000 (reserved)
[    0.000000]  modified: 0000000000100000 - 000000000ffed000 (usable)
[    0.000000]  modified: 000000000ffed000 - 0000000010000000 (reserved)
[    0.000000] initial memory mapped : 0 - 00c00000
[    0.000000] init_memory_mapping: 0000000000000000-000000000ffed000
[    0.000000] Using x86 segment limits to approximate NX protection
[    0.000000]  0000000000 - 0000400000 page 4k
[    0.000000]  0000400000 - 000fc00000 page 2M
[    0.000000]  000fc00000 - 000ffed000 page 4k
[    0.000000] kernel direct mapping tables up to ffed000 @ 7000-c000
[    0.000000] RAMDISK: 0f846000 - 0ffdcf5b
[    0.000000] ACPI Error: A valid RSDP was not found
(20090903/tbxfroot-219)
[    0.000000] 0MB HIGHMEM available.
[    0.000000] 255MB LOWMEM available.
[    0.000000]   mapped low ram: 0 - 0ffed000
[    0.000000]   low ram: 0 - 0ffed000
[    0.000000]   node 0 low ram: 00000000 - 0ffed000
[    0.000000]   node 0 bootmap 00008000 - 0000a000
[    0.000000] (9 early reservations) ==> bootmem [0000000000 - 000ffed000]
[    0.000000]   #0 [0000000000 - 0000001000]   BIOS data page ==>
[0000000000 - 0000001000]
[    0.000000]   #1 [0000001000 - 0000002000]    EX TRAMPOLINE ==>
[0000001000 - 0000002000]
[    0.000000]   #2 [0000006000 - 0000007000]       TRAMPOLINE ==>
[0000006000 - 0000007000]
[    0.000000]   #3 [0000100000 - 00008d9e98]    TEXT DATA BSS ==>
[0000100000 - 00008d9e98]
[    0.000000]   #4 [000f846000 - 000ffdcf5b]          RAMDISK ==>
[000f846000 - 000ffdcf5b]
[    0.000000]   #5 [000009f000 - 0000100000]    BIOS reserved ==>
[000009f000 - 0000100000]
[    0.000000]   #6 [00008da000 - 00008dd049]              BRK ==>
[00008da000 - 00008dd049]
[    0.000000]   #7 [0000007000 - 0000008000]          PGTABLE ==>
[0000007000 - 0000008000]
[    0.000000]   #8 [0000008000 - 000000a000]          BOOTMAP ==>
[0000008000 - 000000a000]
[    0.000000] Zone PFN ranges:
[    0.000000]   DMA      0x00000000 -> 0x00001000
[    0.000000]   Normal   0x00001000 -> 0x0000ffed
[    0.000000]   HighMem  0x0000ffed -> 0x0000ffed
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[3] active PFN ranges
[    0.000000]     0: 0x00000000 -> 0x00000002
[    0.000000]     0: 0x00000006 -> 0x0000009f
[    0.000000]     0: 0x00000100 -> 0x0000ffed
[    0.000000] On node 0 totalpages: 65416
[    0.000000] free_area_init_node: node 0, pgdat c0798720, node_mem_map
c1001000
[    0.000000]   DMA zone: 32 pages used for memmap
[    0.000000]   DMA zone: 0 pages reserved
[    0.000000]   DMA zone: 3963 pages, LIFO batch:0
[    0.000000]   Normal zone: 480 pages used for memmap
[    0.000000]   Normal zone: 60941 pages, LIFO batch:15
[    0.000000] Using APIC driver default
[    0.000000] SFI: Simple Firmware Interface v0.7 http://simplefirmware.org
[    0.000000] SMP: Allowing 1 CPUs, 0 hotplug CPUs
[    0.000000] Found and enabled local APIC!
[    0.000000] nr_irqs_gsi: 16
[    0.000000] PM: Registered nosave memory: 0000000000002000 -
0000000000006000
[    0.000000] PM: Registered nosave memory: 000000000009f000 -
00000000000a0000
[    0.000000] PM: Registered nosave memory: 00000000000a0000 -
00000000000f0000
[    0.000000] PM: Registered nosave memory: 00000000000f0000 -
0000000000100000
[    0.000000] Allocating PCI resources starting at 10000000 (gap:
10000000:f0000000)
[    0.000000] Booting paravirtualized kernel on bare hardware
[    0.000000] NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:1 nr_node_ids:1
[    0.000000] PERCPU: Embedded 14 pages/cpu @c1400000 s36024 r0 d21320
u4194304
[    0.000000] pcpu-alloc: s36024 r0 d21320 u4194304 alloc=1*4194304
[    0.000000] pcpu-alloc: [0] 0
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total
pages: 64904
[    0.000000] Kernel command line:
root=UUID=0d89b7e3-b0c6-4b5c-bbc5-9b33670a5aef ro
[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072
bytes)
[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Enabling fast FPU save and restore... done.
[    0.000000] Enabling unmasked SIMD FPU exception support... done.
[    0.000000] Initializing CPU#0
[    0.000000] allocated 1310340 bytes of page_cgroup
[    0.000000] please try 'cgroup_disable=memory' option if you don't want
memory cgroups
[    0.000000] Initializing HighMem for node 0 (00000000:00000000)
[    0.000000] Memory: 242004k/262068k available (4673k kernel code, 19456k
reserved, 2121k data, 656k init, 0k highmem)
[    0.000000] virtual kernel memory layout:
[    0.000000]     fixmap  : 0xfff1d000 - 0xfffff000   ( 904 kB)
[    0.000000]     pkmap   : 0xff800000 - 0xffc00000   (4096 kB)
[    0.000000]     vmalloc : 0xd07ed000 - 0xff7fe000   ( 752 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xcffed000   ( 255 MB)
[    0.000000]       .init : 0xc07a3000 - 0xc0847000   ( 656 kB)
[    0.000000]       .data : 0xc0590653 - 0xc07a2e48   (2121 kB)
[    0.000000]       .text : 0xc0100000 - 0xc0590653   (4673 kB)
[    0.000000] Checking if this processor honours the WP bit even in
supervisor mode...Ok.
[    0.000000] SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0,
CPUs=1, Nodes=1
[    0.000000] Hierarchical RCU implementation.
[    0.000000] NR_IRQS:2304 nr_irqs:256
[    0.000000] Console: colour dummy device 80x25
[    0.000000] console [tty0] enabled
[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 451.012 MHz processor.
[    0.004015] Calibrating delay loop (skipped), value calculated using
timer frequency.. 902.02 BogoMIPS (lpj=1804048)
[    0.004136] Security Framework initialized
[    0.004283] AppArmor: AppArmor initialized
[    0.004352] Mount-cache hash table entries: 512
[    0.004983] Initializing cgroup subsys ns
[    0.005027] Initializing cgroup subsys cpuacct
[    0.005067] Initializing cgroup subsys memory
[    0.005130] Initializing cgroup subsys devices
[    0.005161] Initializing cgroup subsys freezer
[    0.005187] Initializing cgroup subsys net_cls
[    0.005304] CPU: L1 I cache: 16K, L1 D cache: 16K
[    0.005341] CPU: L2 cache: 512K
[    0.005365] CPU serial number disabled.
[    0.005395] mce: CPU supports 5 MCE banks
[    0.005477] Performance Events: p6 PMU driver.
[    0.005600] ... version:                0
[    0.005624] ... bit width:              32
[    0.005647] ... generic registers:      2
[    0.005671] ... value mask:             00000000ffffffff
[    0.005699] ... max period:             000000007fffffff
[    0.005725] ... fixed-purpose events:   0
[    0.005749] ... event mask:             0000000000000003
[    0.005783] Checking 'hlt' instruction... OK.
[    0.022222] SMP alternatives: switching to UP code
[    0.048806] Freeing SMP alternatives: 19k freed
[    0.048923] ftrace: converting mcount calls to 0f 1f 44 00 00
[    0.048988] ftrace: allocating 21771 entries in 43 pages
[    0.052421] Enabling APIC mode:  Flat.  Using 0 I/O APICs
[    0.052491] weird, boot CPU (#0) not listed by the BIOS.
[    0.052517] SMP motherboard not detected.
[    0.052548] Enabling APIC mode:  Flat.  Using 0 I/O APICs
[    0.160037] SMP disabled
[    0.161307] Brought up 1 CPUs
[    0.161347] Total of 1 processors activated (902.02 BogoMIPS).
[    0.163187] CPU0 attaching NULL sched-domain.
[    0.164001] devtmpfs: initialized
[    0.166250] regulator: core version 0.5
[    0.166333] Time: 18:40:43  Date: 05/14/10
[    0.166635] NET: Registered protocol family 16
[    0.167340] EISA bus registered
[    0.168534] PCI: PCI BIOS revision 2.10 entry at 0xffe77, last bus=1
[    0.168569] PCI: Using configuration type 1 for base access
[    0.174596] bio: create slab <bio-0> at 0
[    0.174971] ACPI: Interpreter disabled.
[    0.175313] vgaarb: loaded
[    0.175986] SCSI subsystem initialized
[    0.176328] libata version 3.00 loaded.
[    0.176804] usbcore: registered new interface driver usbfs
[    0.176912] usbcore: registered new interface driver hub
[    0.177154] usbcore: registered new device driver usb
[    0.177969] PCI: Probing PCI hardware
[    0.178004] PCI: Probing PCI hardware (bus 00)
[    0.178176] pci 0000:00:00.0: reg 10 32bit mmio pref:
[0xe0000000-0xefffffff]
[    0.178474] pci 0000:00:04.1: reg 20 io port: [0x1020-0x102f]
[    0.178586] pci 0000:00:04.2: reg 20 io port: [0x1000-0x101f]
[    0.178655] * Found PM-Timer Bug on the chipset. Due to workarounds for a
bug,
[    0.178664] * this clock source is slow. Consider trying other clock
sources
[    0.178793] pci 0000:00:04.3: quirk: region 0f00-0f0f claimed by PIIX4
SMB
[    0.179873] pci 0000:00:04.0: PIIX/ICH IRQ router [8086:7110]
[    0.180534] NetLabel: Initializing
[    0.180568] NetLabel:  domain hash size = 128
[    0.180590] NetLabel:  protocols = UNLABELED CIPSOv4
[    0.180679] NetLabel:  unlabeled traffic allowed by default
[    0.180901] Switching to clocksource tsc
[    0.190446] AppArmor: AppArmor Filesystem Enabled
[    0.190513] pnp: PnP ACPI: disabled
[    0.190539] PnPBIOS: Scanning system for PnP BIOS support...
[    0.190675] PnPBIOS: Found PnP BIOS installation structure at 0xc00f71b0
[    0.190711] PnPBIOS: PnP BIOS version 1.0, entry 0xf0000:0xdf0c, dseg
0xf0000
[    0.192416] PnPBIOS: dev_node_info: function not supported on this system
[    0.192448] PnPBIOS: Unable to get node info.  Aborting.
[    0.193710] pci 0000:00:01.0: PCI bridge, secondary bus 0000:01
[    0.193749] pci 0000:00:01.0:   IO window: disabled
[    0.193781] pci 0000:00:01.0:   MEM window: disabled
[    0.193810] pci 0000:00:01.0:   PREFETCH window: disabled
[    0.193869] pci_bus 0000:00: resource 0 io:  [0x00-0xffff]
[    0.193885] pci_bus 0000:00: resource 1 mem: [0x000000-0xffffffff]
[    0.194077] NET: Registered protocol family 2
[    0.194659] IP route cache hash table entries: 2048 (order: 1, 8192
bytes)
[    0.196481] TCP established hash table entries: 8192 (order: 4, 65536
bytes)
[    0.196868] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.197208] TCP: Hash tables configured (established 8192 bind 8192)
[    0.197249] TCP reno registered
[    0.197681] NET: Registered protocol family 1
[    0.197795] pci 0000:00:00.0: Limiting direct PCI/PCI transfers
[    0.198372] platform rtc_cmos: registered platform RTC device (no PNP
device found)
[    0.198681] cpufreq-nforce2: No nForce2 chipset.
[    0.198919] Scanning for low memory corruption every 60 seconds
[    0.199665] audit: initializing netlink socket (disabled)
[    0.199741] type=2000 audit(1273862443.198:1): initialized
[    0.247383] Trying to unpack rootfs image as initramfs...
[    0.299773] HugeTLB registered 4 MB page size, pre-allocated 0 pages
[    0.320818] VFS: Disk quotas dquot_6.5.2
[    0.321284] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    0.331768] fuse init (API version 7.13)
[    0.332524] msgmni has been set to 473
[    0.333988] alg: No test for stdrng (krng)
[    0.334236] Block layer SCSI generic (bsg) driver version 0.4 loaded
(major 253)
[    0.334281] io scheduler noop registered
[    0.334305] io scheduler anticipatory registered
[    0.334329] io scheduler deadline registered
[    0.334693] io scheduler cfq registered (default)
[    0.335231] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[    0.335400] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
[    0.343676] isapnp: Scanning for PnP cards...
[    0.404738] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    0.405042] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    0.405346] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
[    0.420918] brd: module loaded
[    0.428433] loop: module loaded
[    0.429052] input: Macintosh mouse button emulation as
/devices/virtual/input/input0
[    0.429672] ata_piix 0000:00:04.1: version 2.13
[    0.436755] scsi0 : ata_piix
[    0.437400] scsi1 : ata_piix
[    0.437652] ata1: PATA max UDMA/33 cmd 0x1f0 ctl 0x3f6 bmdma 0x1020 irq
14
[    0.437696] ata2: PATA max UDMA/33 cmd 0x170 ctl 0x376 bmdma 0x1028 irq
15
[    0.440077] Fixed MDIO Bus: probed
[    0.440338] PPP generic driver version 2.4.2
[    0.440650] tun: Universal TUN/TAP device driver, 1.6
[    0.440685] tun: (C) 1999-2004 Max Krasnyansky 
[    0.441304] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    0.441441] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    0.441548] uhci_hcd: USB Universal Host Controller Interface driver
[    0.441750] PCI: setting IRQ 5 as level-triggered
[    0.441768] uhci_hcd 0000:00:04.2: assigned PCI INT D -> IRQ 5
[    0.441851] uhci_hcd 0000:00:04.2: UHCI Host Controller
[    0.442138] uhci_hcd 0000:00:04.2: new USB bus registered, assigned bus
number 1
[    0.442249] uhci_hcd 0000:00:04.2: irq 5, io base 0x00001000
[    0.448381] usb usb1: configuration #1 chosen from 1 choice
[    0.448630] hub 1-0:1.0: USB hub found
[    0.448713] hub 1-0:1.0: 2 ports detected
[    0.449203] PNP: No PS/2 controller found. Probing ports directly.
[    0.451622] serio: i8042 KBD port at 0x60,0x64 irq 1
[    0.451683] serio: i8042 AUX port at 0x60,0x64 irq 12
[    0.452541] mice: PS/2 mouse device common for all mice
[    0.453252] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0
[    0.453334] rtc0: alarms up to one day, 114 bytes nvram
[    0.454009] device-mapper: uevent: version 1.0.3
[    0.460126] device-mapper: ioctl: 4.15.0-ioctl (2009-04-01) initialised:
[e-mail]
[    0.460631] device-mapper: multipath: version 1.1.0 loaded
[    0.460671] device-mapper: multipath round-robin: version 1.0.0 loaded
[    0.461617] EISA: Probing bus 0 at eisa.0
[    0.461666] Cannot allocate resource for EISA slot 1
[    0.461739] EISA: Detected 0 cards.
[    0.468110] cpuidle: using governor ladder
[    0.468151] cpuidle: using governor menu
[    0.471123] TCP cubic registered
[    0.472332] NET: Registered protocol family 10
[    0.475324] lo: Disabled Privacy Extensions
[    0.477413] NET: Registered protocol family 17
[    0.477615] Using IPI No-Shortcut mode
[    0.478245] PM: Resume from disk failed.
[    0.478315] registered taskstats version 1
[    0.478700]   Magic number: 10:88:696
[    0.483251] rtc_cmos rtc_cmos: setting system clock to 2010-05-14
18:40:43 UTC (1273862443)
[    0.483309] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found
[    0.483335] EDD information not available.
[    0.627564] ata2.00: ATA-5: MAXTOR 6L060J3, A93.0500, max UDMA/133
[    0.627626] ata2.00: 117266688 sectors, multi 0: LBA
[    0.644925] ata2.00: configured for UDMA/33
[    0.796025] usb 1-1: new low speed USB device using uhci_hcd and address
2
[    1.059638] isapnp: No Plug & Play device found
[    1.060471] scsi 1:0:0:0: Direct-Access     ATA      MAXTOR 6L060J3
A93. PQ: 0 ANSI: 5
[    1.061301] sd 1:0:0:0: [sda] 117266688 512-byte logical blocks: (60.0
GB/55.9 GiB)
[    1.061784] sd 1:0:0:0: [sda] Write Protect is off
[    1.061822] sd 1:0:0:0: [sda] Mode Sense: 00 3a 00 00
[    1.062057] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled,
doesn't support DPO or FUA
[    1.062939] sd 1:0:0:0: Attached scsi generic sg0 type 0
[    1.063932]  sda: sda1 sda2 <
[    1.076867] usb 1-1: configuration #1 chosen from 1 choice
[    1.083491]  sda5 sda6 sda7 sda8 sda9 >
[    1.112007] sd 1:0:0:0: [sda] Attached SCSI disk
[    1.199037] usb 1-2: new full speed USB device using uhci_hcd and address
3
[    1.502189] usb 1-2: configuration #1 chosen from 1 choice
[    1.848042] Freeing initrd memory: 7771k freed
[    1.898959] Freeing unused kernel memory: 656k freed
[    1.903230] Write protecting the kernel text: 4676k
[    1.903476] Write protecting the kernel read-only data: 1840k
[    2.004050] udev: starting version 151
[    2.885768] usbcore: registered new interface driver hiddev
[    2.904300] input: CHESEN PS2 to USB Converter as
/devices/pci0000:00/0000:00:04.2/usb1/1-1/1-1:1.0/input/input1
[    2.905308] generic-usb 0003:0A81:0205.0001: input,hidraw0: USB HID v1.10
Keyboard [CHESEN PS2 to USB Converter] on usb-0000:00:04.2-1/input0
[    2.940965] input: CHESEN PS2 to USB Converter as
/devices/pci0000:00/0000:00:04.2/usb1/1-1/1-1:1.1/input/input2
[    2.942346] generic-usb 0003:0A81:0205.0002: input,hidraw1: USB HID v1.10
Mouse [CHESEN PS2 to USB Converter] on usb-0000:00:04.2-1/input1
[    2.942575] usbcore: registered new interface driver usbhid
[    2.943329] usbhid: v2.6:USB HID core driver
[    3.268987] kjournald starting.  Commit interval 5 seconds
[    3.269085] EXT3-fs: mounted filesystem with ordered data mode.
[    5.087080] Adding 546168k swap on /dev/sda7.  Priority:-1 extents:1
across:546168k
[    5.393459] udev: starting version 151
[    6.738214] Linux agpgart interface v0.103
[    6.774038] piix4_smbus 0000:00:04.3: SMBus Host Controller at 0xf00,
revision 0
[    6.810496] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[    7.202720] cfg80211: Calling CRDA to update world regulatory domain
[    7.531468] agpgart-intel 0000:00:00.0: Intel 440BX Chipset
[    7.558761] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xe0000000
[    7.908460] lp: driver loaded but no devices found
[    8.368553] type=1505 audit(1273862451.384:2):  operation="profile_load"
pid=354 name="/sbin/dhclient3"
[    8.370919] type=1505 audit(1273862451.384:3):  operation="profile_load"
pid=354 name="/usr/lib/NetworkManager/nm-dhcp-client.action"
[    8.372448] type=1505 audit(1273862451.388:4):  operation="profile_load"
pid=354 name="/usr/lib/connman/scripts/dhclient-script"
[    8.714474] phy0: Selected rate control algorithm 'minstrel'
[    8.718902] Registered led device: rt73usb-phy0::radio
[    8.719017] Registered led device: rt73usb-phy0::assoc
[    8.719132] Registered led device: rt73usb-phy0::quality
[    8.721625] usbcore: registered new interface driver rt73usb
[    9.360013] EXT3 FS on sda1, internal journal
[    9.731481] kjournald starting.  Commit interval 5 seconds
[    9.756569] EXT3 FS on sda8, internal journal
[    9.756594] EXT3-fs: mounted filesystem with ordered data mode.
[   10.163421] kjournald starting.  Commit interval 5 seconds
[   10.176756] EXT3 FS on sda9, internal journal
[   10.176783] EXT3-fs: mounted filesystem with ordered data mode.
[   10.507208] kjournald starting.  Commit interval 5 seconds
[   10.509881] EXT3 FS on sda5, internal journal
[   10.509909] EXT3-fs: mounted filesystem with ordered data mode.
[   10.807777] kjournald starting.  Commit interval 5 seconds
[   10.808380] EXT3 FS on sda6, internal journal
[   10.808406] EXT3-fs: mounted filesystem with ordered data mode.
[   11.618890] type=1503 audit(1273862454.632:5):  operation="capable"
pid=475 parent=474 profile="/sbin/dhclient3" name="net_admin"
[   12.586880] type=1505 audit(1273862455.600:6):
operation="profile_replace" pid=514 name="/sbin/dhclient3"
[   12.589305] type=1505 audit(1273862455.604:7):
operation="profile_replace" pid=514
name="/usr/lib/NetworkManager/nm-dhcp-client.action"
[   12.590708] type=1505 audit(1273862455.604:8):
operation="profile_replace" pid=514
name="/usr/lib/connman/scripts/dhclient-script"
[   12.726956] type=1505 audit(1273862455.740:9):  operation="profile_load"
pid=515 name="/usr/sbin/tcpdump"
[   12.807711] rt73usb 1-2:1.0: firmware: requesting rt73.bin
[   13.222925] ADDRCONF(NETDEV_UP): wlan0: link is not ready
[   16.080416] wlan0: deauthenticating from <snip> by local choice
(reason=3)
[   16.087267] wlan0: direct probe to AP <snip> (try 1)
[   16.090623] wlan0: direct probe responded
[   16.090812] wlan0: authenticate with AP <snip> (try 1)
[   16.093520] wlan0: authenticated
[   16.093636] wlan0: associate with AP <snip> (try 1)
[   16.097190] wlan0: RX AssocResp from <snip> (capab=0x431 status=0 aid=9)
[   16.097208] wlan0: associated
[   16.154528] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready
[   16.154748] cfg80211: Calling CRDA for country: DE
[   16.285828] cfg80211: Received country IE:
[   16.285849] cfg80211: Regulatory domain: DE
[   16.285859]  (start_freq - end_freq @ bandwidth), (max_antenna_gain,
max_eirp)
[   16.285877]  (2402000 KHz - 2494000 KHz @ 40000 KHz), (10000 mBi, 10000
mBm)
[   16.285889] cfg80211: CRDA thinks this should applied:
[   16.285899] cfg80211: Regulatory domain: DE
[   16.285908]  (start_freq - end_freq @ bandwidth), (max_antenna_gain,
max_eirp)
[   16.285923]  (2400000 KHz - 2483500 KHz @ 40000 KHz), (N/A, 2000 mBm)
[   16.285939]  (5150000 KHz - 5350000 KHz @ 40000 KHz), (N/A, 2000 mBm)
[   16.285954]  (5470000 KHz - 5725000 KHz @ 40000 KHz), (N/A, 2698 mBm)
[   16.285964] cfg80211: We intersect both of these and get:
[   16.285975] cfg80211: Regulatory domain: 98
[   16.285984]  (start_freq - end_freq @ bandwidth), (max_antenna_gain,
max_eirp)
[   16.285999]  (2402000 KHz - 2483500 KHz @ 40000 KHz), (N/A, 2000 mBm)
[   16.286028] cfg80211: Disabling channel 2484 MHz on phy0 due to Country
IE
[   16.286049] cfg80211: Current regulatory domain updated by AP to: DE
[   16.286060]  (start_freq - end_freq @ bandwidth), (max_antenna_gain,
max_eirp)
[   16.286076]  (2402000 KHz - 2483500 KHz @ 40000 KHz), (N/A, 2000 mBm)
[   17.372795] padlock: VIA PadLock not detected.
[   26.936735] wlan0: no IPv6 routers present

[PATCH] SECC Pentium 2/3 users are gonna love this

[ron minnich]

Forgive my ignorance, but are there super-compact boards that use this
hardware?

some kind of low-cost low power thing? Or are there just old systems :-)

thanks

ron

[PATCH] SECC Pentium 2/3 users are gonna love this

[Keith Hui]

ping... Is this too much? :-)

On Thu, May 13, 2010 at 10:03 PM, Keith Hui  wrote:
> Hi all,
>
> This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other
> related changes (below), so it is gzipped. I may have committed a few
> "crimes" here, but anyway...
> This patch:
> Brings back L2 initialization from coreboot v1 for family 63x,65x
>
> and 67x CPUs. Need someone with a Mendocino Celeron to see if the
> entire 128k of L2 is still enabled.
> 2. Split model_67x/65x and model_63x from model_6xx. model_67x also
> serves model 65x because they share too much code. Also included are
> Intel microcode for all CPUs in these families. There's just one file
> for all microcodes in one family.
> 3. In Slot 1 Makefile.inc, conditionally bring in sources in models
> 63x/67x/6bx only when the proper config has been selected in Kconfig.
> Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has
> been selected.
> 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the
> mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above.
> 5. Blocked out some apparently unused #includes from model_6xx_init.c.
> Once we're sure nothing really are using it, then remove them.
>
> Bootlog with a PIII 600MHz can be found here:
> http://coreboot.pastebin.com/PNUzJXZT

[PATCH] SECC Pentium 2/3 users are gonna love this

[Stefan Reinauer]

> ping... Is this too much? :-)

Please don't gzip patches, it lowers the chance of someone reviewing
them to zero ;-)

There is 65x microcode in the model_67x directory, and it's not split up
into single files as for the other CPUs.

+ if (cpuid_res.ebx != 0x756e6547 || cpuid_res.edx != 0x49656e69 ||
cpuid_res.ecx != 0x6c65746e) {
+ printk(BIOS_INFO, "Not 'GenuineIntel' Processor");
+ return 0;
+ }

This is not necessary. When model_6**_init() is executed, it's clear
already that this is an intel cpu.

+/* if (signature & 0x1000) {
+ printk(BIOS_DEBUG,"Overdrive chip no L2 cache configuration\n");
+ return 0;
+ }
+
+ if (signature < 0x630 || signature >= 0x680) {
+ printk(BIOS_DEBUG,"L2 cache on CPUID %x does not require
configuration\n", signature);
+ return 0;
+ }*/

I think this code should just be dropped

Is it generally possible to move p6_configure_l2_cache to a generic
place, maybe to cpu/x86/cache ?

+/*--- End L2 init code from corebbot v1 ---*/

I think this kind of comment is not needed.

+static inline void strcpy(char *dst, char *src)
+{
+ while (*src) *dst++ = *src++;
+}

I know I am the idiot who introduced this in a model_xxx_init.c file,
but maybe we should move it to lib/strcpy.c ?

+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, 0x0650 },
+ { X86_VENDOR_INTEL, 0x0651 },
+ { X86_VENDOR_INTEL, 0x0652 },
+ { X86_VENDOR_INTEL, 0x0653 },
+ { X86_VENDOR_INTEL, 0x0671 },
+ { X86_VENDOR_INTEL, 0x0672 },
+ { X86_VENDOR_INTEL, 0x0673 },
+ { 0, 0 },
+};

Instead of using a common driver, can two drivers use a common set of
shared functions instead?

+ifeq ($(CONFIG_USE_DCACHE_RAM),y)
+cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+endif

This will break all targets except the ones you worked on.

Stefan
> On Thu, May 13, 2010 at 10:03 PM, Keith Hui  wrote:
> > Hi all,
> >
> > This is it. The 72oz steak. ;-) It is ~180k seasoned with a few other
> > related changes (below), so it is gzipped. I may have committed a few
> > "crimes" here, but anyway...
> > This patch:
> > Brings back L2 initialization from coreboot v1 for family 63x,65x
> >
> > and 67x CPUs. Need someone with a Mendocino Celeron to see if the
> > entire 128k of L2 is still enabled.
> > 2. Split model_67x/65x and model_63x from model_6xx. model_67x also
> > serves model 65x because they share too much code. Also included are
> > Intel microcode for all CPUs in these families. There's just one file
> > for all microcodes in one family.
> > 3. In Slot 1 Makefile.inc, conditionally bring in sources in models
> > 63x/67x/6bx only when the proper config has been selected in Kconfig.
> > Also, only include cache_as_ram.inc if USE_DCACHE_RAM (ie. CAR) has
> > been selected.
> > 4. Remove USE_DCACHE_RAM from Slot 1 Kconfig. They should be in the
> > mainboards. Add CPU_INTEL_MODEL_6xX Kconfigs needed for (3) above.
> > 5. Blocked out some apparently unused #includes from model_6xx_init.c.
> > Once we're sure nothing really are using it, then remove them.
> >
> > Bootlog with a PIII 600MHz can be found here:
> > http://coreboot.pastebin.com/PNUzJXZT