#137: S2895 no function after coreboot 2 flash

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coreboot

18 May 2009 18 May '09

7:17 p.m.

#137: S2895 no function after coreboot 2 flash --------------------------+------------------------------------------------- Reporter: anonymous | Type: defect Status: new | Priority: major Milestone: | Component: buildrom Version: v2 | Keywords: Dependencies: | Patchstatus: there is no patch --------------------------+------------------------------------------------- Hi Guys,

I am not sure whether i am correct here with you guys. But i have some troubles after flashing the tyan-s2895.rom that has been generated with seabios as payload by the buildrom tool. There are no logs in the log folders and everything worked fine. But after flashing the coreboot bios to the board using "flashrom -v -w tyan-s2895.rom" and i "halt" the system, it will come up for a second and switches off immediately. I tried clearing the CMOS, but this did not solve the problem.

Any idea what i am doing wrong?

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137 coreboot http://www.coreboot.org/

Show replies by date

Myles Watson

18 May 18 May

8:01 p.m.

...

I am not sure whether i am correct here with you guys. But i have some troubles after flashing the tyan-s2895.rom that has been generated with seabios as payload by the buildrom tool. There are no logs in the log folders and everything worked fine. But after flashing the coreboot bios to the board using "flashrom -v -w tyan-s2895.rom" and i "halt" the system, it will come up for a second and switches off immediately. I tried clearing the CMOS, but this did not solve the problem.

Any idea what i am doing wrong?

No.

I built an s2895 image just now from buildrom and there is serial output, the display gets initialized, and then it breaks because the version of coreboot is so old in buildrom. Buildrom still uses r3259 for s2895, and a lot has changed since then.

Hopefully you have a way to get your machine back. I like the pushpin method of changing the ROM chips.

Thanks, Myles

Peter Stuge

11:54 p.m.

Myles Watson wrote:

...

...
Any idea what i am doing wrong?

No.

Unfortunately I don't think replies on the list will go back to the Trac poster.

At any rate, Myles, maybe you should bump the coreboot rev for s2895 in buildrom to the one you have confirmed working?

//Peter

Myles Watson

19 May 19 May

2:04 p.m.

...

Unfortunately I don't think replies on the list will go back to the Trac poster.

Yes. I thought he'd read the list for replies.

...

At any rate, Myles, maybe you should bump the coreboot rev for s2895 in buildrom to the one you have confirmed working?

I've never gotten a failover image to work on s2895. I always strip out failover. Is failover really going to go away some day?

Thanks, Myles

Myles Watson

6:42 p.m.

...

At any rate, Myles, maybe you should bump the coreboot rev for s2895 in buildrom to the one you have confirmed working?

I always argued for buildrom using the latest version of Coreboot. In this case the payload (SeaBIOS) continued to evolve.

I guess there's no good way around bit rot. I'm hoping that we'll continue to improve the v2 build process enough that there will be no need for buildrom except to build payloads.

Thanks, Myles

Ward Vandewege

6:49 p.m.

On Tue, May 19, 2009 at 12:42:18PM -0600, Myles Watson wrote:

...

...
At any rate, Myles, maybe you should bump the coreboot rev for s2895 in buildrom to the one you have confirmed working?

I always argued for buildrom using the latest version of Coreboot. In this case the payload (SeaBIOS) continued to evolve.

Yeah - but having a 'known good' combination in buildrom is quite useful too.

...

I guess there's no good way around bit rot. I'm hoping that we'll continue to improve the v2 build process enough that there will be no need for buildrom except to build payloads.

Yep. I want to/need to take a stab at converting buildrom to use CBFS. Ah, time...

Thanks, Ward.

-- Ward Vandewege ward@fsf.org Free Software Foundation - Senior Systems Administrator

Myles Watson

6:55 p.m.

On Tue, May 19, 2009 at 12:49 PM, Ward Vandewege ward@gnu.org wrote:

...

On Tue, May 19, 2009 at 12:42:18PM -0600, Myles Watson wrote:

...
...
At any rate, Myles, maybe you should bump the coreboot rev for s2895 in buildrom to the one you have confirmed working?

I always argued for buildrom using the latest version of Coreboot. In this case the payload (SeaBIOS) continued to evolve.

Yeah - but having a 'known good' combination in buildrom is quite useful too.

That's what I'm saying. Since we don't have SeaBIOS versioned (we would have had to bump it many times since January), It wasn't known good anymore. I don't see an easy solution since we have so few buildrom users to scream when things break.

...

...
I guess there's no good way around bit rot. I'm hoping that we'll continue to improve the v2 build process enough that there will be no need for buildrom except to build payloads.

Yep. I want to/need to take a stab at converting buildrom to use CBFS. Ah, time...

Thanks, Myles

Ward Vandewege

6:59 p.m.

On Tue, May 19, 2009 at 12:55:19PM -0600, Myles Watson wrote:

...

On Tue, May 19, 2009 at 12:49 PM, Ward Vandewege ward@gnu.org wrote:

...
On Tue, May 19, 2009 at 12:42:18PM -0600, Myles Watson wrote:

...
...
At any rate, Myles, maybe you should bump the coreboot rev for s2895 in buildrom to the one you have confirmed working?

I always argued for buildrom using the latest version of Coreboot. In this case the payload (SeaBIOS) continued to evolve.

Yeah - but having a 'known good' combination in buildrom is quite useful too.

That's what I'm saying. Since we don't have SeaBIOS versioned (we would have had to bump it many times since January), It wasn't known good anymore. I don't see an easy solution since we have so few buildrom users to scream when things break.

Ah - sorry, the problem is that we track HEAD for seabios. Can't we just use a git revision number for seabios?

Thanks, Ward.

-- Ward Vandewege ward@fsf.org Free Software Foundation - Senior Systems Administrator

Myles Watson

7:10 p.m.

...

...
That's what I'm saying. Since we don't have SeaBIOS versioned (we would have had to bump it many times since January), It wasn't known good anymore. I don't see an easy solution since we have so few buildrom users to scream when things break.

Ah - sorry, the problem is that we track HEAD for seabios. Can't we just use a git revision number for seabios?

We could. I guess the biggest problem is that we don't track known good payloads per platform. Someone could try the latest SeaBIOS on qemu and bump up the revision. If that broke everyone else... After several bumps where it worked on different platforms it would be hard to figure out what happened.

I guess since I don't have a good solution I'm just whining :)

Thanks, Myles

coreboot

9:16 a.m.

Comment(by anonymous):

By the way... I have recovered my board with the original Bios chip. The same problem appears every time i flash the coreboot ROM. It does not matter if i use a hardware EEPROM burner or the flashrom utility.

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:1 coreboot http://www.coreboot.org/

coreboot

4:08 p.m.

Comment(by myles):

I'll help you work through it. Before we continue, though, you should know that Nvidia's ck804 SATA isn't supported by any payloads. If you want to boot from a SATA drive you'll have to put Linux in the ROM (Linux- As-Bootloader). PATA works fine.

Thanks, Myles

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:2 coreboot http://www.coreboot.org/

Ward Vandewege

4:14 p.m.

On Tue, May 19, 2009 at 04:08:01PM -0000, coreboot wrote:

...

#137: S2895 no function after coreboot 2 flash --------------------------+------------------------------------------------- Reporter: anonymous | Type: defect Status: new | Priority: major Milestone: | Component: buildrom Version: v2 | Keywords: Dependencies: | Patchstatus: there is no patch --------------------------+-------------------------------------------------

Comment(by myles):

I'll help you work through it. Before we continue, though, you should know that Nvidia's ck804 SATA isn't supported by any payloads. If you want to boot from a SATA drive you'll have to put Linux in the ROM (Linux- As-Bootloader). PATA works fine.

Hmmm. s2891 is also ck804 based, and there FILO works fine for me?

Thanks, Ward.

-- Ward Vandewege ward@fsf.org Free Software Foundation - Senior Systems Administrator

Myles Watson

5:45 p.m.

...

...
I'll help you work through it. Before we continue, though, you should know that Nvidia's ck804 SATA isn't supported by any payloads. If you want to boot from a SATA drive you'll have to put Linux in the ROM

(Linux-

...
As-Bootloader). PATA works fine.

Hmmm. s2891 is also ck804 based, and there FILO works fine for me?

With a SATA drive? I've never gotten that to work. I thought that since ck804 doesn't have a compatibility mode, you'd have to port the driver from Linux.

Thanks, Myles

Ward Vandewege

5:55 p.m.

On Tue, May 19, 2009 at 11:45:50AM -0600, Myles Watson wrote:

...

...
...
I'll help you work through it. Before we continue, though, you should know that Nvidia's ck804 SATA isn't supported by any payloads. If you want to boot from a SATA drive you'll have to put Linux in the ROM

(Linux-

...
As-Bootloader). PATA works fine.

Hmmm. s2891 is also ck804 based, and there FILO works fine for me?

With a SATA drive? I've never gotten that to work. I thought that since ck804 doesn't have a compatibility mode, you'd have to port the driver from Linux.

Hmm, yes, definitely with a SATA drive. But maybe I'm making that up about FILO - I do use LAB on the s2891's that are in production. I think you are probably right.

Thanks, Ward.

-- Ward Vandewege ward@fsf.org Free Software Foundation - Senior Systems Administrator

coreboot

4:26 p.m.

Comment(by anonymous):

Hi Myles,

Thanks a lot for your fast response. So you are saying that the problem seems to be that i am using a SATA HDD? That could explain a lot. i will try doing an Windows installation on the IDE drive and see if the problem will then be resolved.

About my current config:

I am using the TYAN S2895 with 2 SATA HDDs. first one has Windows on it and the second one is using Suse 11.1. Grub is installed on the first SATA HDD with the Windows.

Any chance to get both OS to work at the same time?

However i will try with an IDE HDD and Windows via seabios first ;-)

BR, Tweek

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:3 coreboot http://www.coreboot.org/

coreboot

5:55 p.m.

Comment(by myles):

I was just warning you. Ward says you might be able to get SATA to work.

I'll update buildrom with something that works for me, then you can try it again. You shouldn't go to the work of installing on different disks until you can get at least some output from your serial port.

Thanks, Myles

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:4 coreboot http://www.coreboot.org/

coreboot

6:36 p.m.

Comment(by anonymous):

Replying to [comment:3 anonymous]:

...

Hi Myles,

Thanks a lot for your fast response. So you are saying that the problem seems to be that i am using a SATA

HDD? It wasn't getting that far.

...

About my current config:

I am using the TYAN S2895 with 2 SATA HDDs. first one has Windows on it

and the second one is using Suse 11.1. Grub is installed on the first SATA HDD with the Windows.

...

Any chance to get both OS to work at the same time?

Booting at the same time isn't a problem, but s2895 needs some ACPI help before Windows will boot. SeaBIOS will find Grub and it will just work for you once Windows boots on s2895.

Try it again and when you do make configure, select Payload Configuration->Enable LZMA Compression. That's the way I tried it. ACPI works well enough for Ubuntu...

Thanks, Myles

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:5 coreboot http://www.coreboot.org/

coreboot

10:59 p.m.

Comment(by anonymous):

So I have have tried it again. With LZMA compression enabled, i get a rom file thats ~500k while without i get 1M rom file. Only the 1M rom file works with the flashrom as the chip is a 49LF080A(SST) with 1M. So far so good. The Bios has been flashed, but no screen. The graphic card does not initialize itself.

I need t0 arrange a pc with serial console to see whats going on.

Thanks for your help. Tweek

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:6 coreboot http://www.coreboot.org/

coreboot

20 May 20 May

2:19 p.m.

Comment(by anonymous):

I have now tested with a serial console but i never get any output on the serial console.

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:7 coreboot http://www.coreboot.org/

coreboot

2:40 p.m.

Comment(by myles):

Replying to [comment:7 anonymous]:

...

I have now tested with a serial console but i never get any output on

the serial console.

Have you tested the compressed version? I know you said it builds a 512K ROM. I thought that was the board default.

cat coreboot.rom coreboot.rom >1M.rom

Or change ROM_SIZE in Config-lab.lb

I think you will get console output with a compressed image.

Myles

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:8 coreboot http://www.coreboot.org/

coreboot

3:13 p.m.

Comment(by anonymous):

The original chip that is on the S2895 is a 1M chip. (SST 49LF080A) If you are interested i can get you a list of what chip comes on which TYAN mainboard. (might be useful for you guys.)

I have tested with what you suggested. That did do the trick. So i used: cat coreboot.rom coreboot.rom >1M.rom And now i get output on my serial console but stops at a certain point. Here is the rest of the output on my serial console. If you need the full log from the console, let me know.

====================================== init keyboard i8042 ctr old=0 new=20 ps2_recvbyte timeout i8042 ctr old=0 new=20 i8042 ctr old=0 new=20 i8042 ctr old=61 new=60 keyboard initialized init lpt Found 1 lpt ports init serial Found 1 serial ports init mouse e820 map has 7 items: 0: 000000000009fc00 - 00000000000a0000 = 2 1: 00000000000f0000 - 0000000000100000 = 2 2: 0910000040004000 - 5254000047004100 = 824200525 3: 000013000f130000 - 100013500f120000 = 335544321 4: ff00000000140013 - 0013001100145012 = 0 5: 0000000020000b20 - 00047f0020000b20 = 127 6: 0000000100000000 - 0000000140000000 = 1 final bios_table_addr: 0x000fb09f (used 104%) bios_table_end_addr overflow!

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:9 coreboot http://www.coreboot.org/

coreboot

3:28 p.m.

Comment(by anonymous):

Replying to [comment:9 anonymous]:

...

The original chip that is on the S2895 is a 1M chip. (SST 49LF080A) If you are interested i can get you a list of what chip comes on which

TYAN mainboard. (might be useful for you guys.) Sure. I'll fix the s2895 config.

...

I have tested with what you suggested. That did do the trick.

Great.

...

Here is the rest of the output on my serial console. If you need the

full log from the console, let me know.

...

e820 map has 7 items: 0: 000000000009fc00 - 00000000000a0000 = 2 1: 00000000000f0000 - 0000000000100000 = 2 2: 0910000040004000 - 5254000047004100 = 824200525 3: 000013000f130000 - 100013500f120000 = 335544321 4: ff00000000140013 - 0013001100145012 = 0 5: 0000000020000b20 - 00047f0020000b20 = 127 6: 0000000100000000 - 0000000140000000 = 1

These values are corrupted. I guess I need to see the whole log.

Thanks, Myles

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:10 coreboot http://www.coreboot.org/

coreboot

3:35 p.m.

Comment(by anonymous):

attached is the logfile. Hope you can help me :-)

Thanks in advance for all your support!

Tweek

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:11 coreboot http://www.coreboot.org/

coreboot

3:49 p.m.

Comment(by myles):

Everything else looks fine, so try setting #define CONFIG_MAX_BIOSTABLE (2048+512)

in work/seabios/seabios-master/src/config.h

...

Thanks in advance for all your support!

No problem.

Thanks, Myles

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:12 coreboot http://www.coreboot.org/

coreboot

8 p.m.

Comment(by anonymous):

I am back with news. It Works!!! I now see my board loading to seabios. The VGA Option ROM initializes itself. Great!

Now that this works so far, i would like to get that Windows XP32 working. As you said, Windows needs some ACPI help. How can i do that?

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:13 coreboot http://www.coreboot.org/

coreboot

11:15 p.m.

Comment(by anonymous):

I am having troubles installing windows. I press F5 during the installation and choose the Standard PC, but it seems that when windos tries to start the scrreen gets corrupt. I attached the picture so you can take a look at it. Think its related to my graphic card?

I tried using a Geforce 8400GS instead of the current Geforce 7200. The 8400 does not show any picture at all while the 7200 worrks fine until windows starts.

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:14 coreboot http://www.coreboot.org/

coreboot

11:15 p.m.

Comment(by anonymous):

I tried using a Geforce 8400GS instead of the current Geforce 7200. The 8400 does not show any picture at all while the 7200 worrks fine until windows starts.

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:14 coreboot http://www.coreboot.org/

coreboot

21 May 21 May

3:20 a.m.

Comment(by myles):

Replying to [comment:13 anonymous]:

...

I am back with news. It Works!!!!

Great.

...

Now that this works so far, i would like to get that Windows XP32

working.

...

As you said, Windows needs some ACPI help. How can i do that?

You can dump the factory ACPI tables and compare them to the ones we have. Because this board has 3 different root PCI buses, it is significantly more complex than the other boards which boot Windows using coreboot.

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:15 coreboot http://www.coreboot.org/

coreboot

11:18 a.m.

Comment(by anonymous):

I need a little more help to get this XP working. Could you give a helping hand? Is it possible to use the DSDT.dat file that i extracted from my original Bios and implement that into the coreboot? Or is this not possible?

BR Tweek

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:16 coreboot http://www.coreboot.org/

coreboot

11:49 a.m.

Comment(by myles):

Replying to [comment:16 anonymous]:

...

I need a little more help to get this XP working. Could you give a

helping hand?

...

Is it possible to use the DSDT.dat file that i extracted from my

original Bios and implement that into the coreboot? Or is this not possible?

It's possible. There are a couple of problems: 1. Buses are renumbered by coreboot 2. Different Opteron registers are used 3. Interrupt assignments are different

I was hoping that the acpica tools and linux firmware kit would help me narrow down the problems. Unfortunately, the ACPI from the factory BIOS has errors too, so it is hard to tell what is right.

I've been thinking about stripping my s2895 down to just one HT link to simplify things, so that I could get Windows to work and then add functionality back in. If we disable the 8131 (you lose PCI-X and possibly SCSI) and disable the Nvidia 2060 (you lose a PCIe slot and a NIC), then there is only one root PCI bus and one APIC. I think it would be doable, but I haven't gotten to it yet.

I'll help you do it if you are interested.

Thanks, Myles

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:17 coreboot http://www.coreboot.org/

coreboot

12:10 p.m.

Comment(by anonymous):

Hi Myles, That sounds great. If i can get my board to work without the PCIx and the second chipset i am fine with that. as i do not use these features of the board.

Tweek

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:18 coreboot http://www.coreboot.org/

coreboot

12:47 p.m.

Comment(by myles):

Replying to [comment:18 anonymous]:

...

Hi Myles, That sounds great. If i can get my board to work without the PCIx and

the second chipset i am fine with that. as i do not use these features of the board.

Great. At this point it probably doesn't make sense to continue this in Trac. Why don't you email me your latest log file, and I'll email you back a patch to simplify the board.

Thanks, Myles mylesgw@gmail.com

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:19 coreboot http://www.coreboot.org/

coreboot

15 Jul 15 Jul

3:42 p.m.

#137: S2895 no function after coreboot 2 flash ----------------------------------------+----------------------------------- Reporter: anonymous | Type: defect Status: closed | Priority: major Milestone: | Component: buildrom Version: v2 | Resolution: fixed Keywords: | Dependencies: Patchstatus: patch has been committed | ----------------------------------------+----------------------------------- Changes (by myles):

* status: new => closed * patchstatus: there is no patch => patch has been committed * resolution: => fixed

-- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/137#comment:20 coreboot http://www.coreboot.org/

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coreboot
Myles Watson
Peter Stuge
Ward Vandewege