X201 porting - coreboot

16 Jan 2013


      Hello, all. I've began porting coreboot to X201 laptop. I've analysed
the original firmware (Phoenix). Video in original firmware is inited by
VGA ROM. The firmware chip is an MX25L6445E SOIC8 package, 8 Mibibytes.
Flashable externally with buspirate but you need an additional power
supply and make sure that cable from chip to buspirate don't exceed ~10cm.
One part of original consists of EFI executables. I've replaced the
executables there with my own and when it ran, the RAM was already
inited but not PCI.
I attach the pcidump and memory maps from normal boot (normalboot.txt)
and when I insert GRUB in BIOS (grubinbios.txt). As you can see the
devices visible in both modes differ. Especially communication
controllers and PCI-PCI bridge. I attach 2 programs: x201_analyze and
x201_reconstruct. With them you can split the original (and create
descriptive XML) and then recreate firmware with changed files. I could
with it also remove files from pack 1 in order to free up some space and
so modified BIOSes continued to boot. lzint code is borrowed from phdeco.
Right now the only working output console is through the use of system
speaker ("spkmodem") and analysing it on another machine. The keyboard
works for input. I've added "spkmodem" to GRUB for this but this code
depends on having calibrated TSC. I'll adjust it to use only PIT instead
and will contribute to coreboot then.
My next step is to remove all parts of original BIOS which are not used
to executed before the point I was able to take over and put in a
coreboot in freed space and launch it from small .efi to take over the
boot at this point. How much more init is needed from this point to
booted kernel? Especially how much new code fro coreboot is needed.
In the next stage I'l be working on eliminating original memory initer
and replace it with coreboot one.
-- 
Regards
Vladimir 'φ-coder/phcoder' Serbinenko