Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "hailfinger" checked in revision 4647 to the coreboot repository. This caused the following changes:
Change Log: r4646 enabled early usage of pci_{read,write}_config{8,16,32}
This allows us to change dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64);
to the much more readable dword = pci_read_config32(sm_dev, 0x64);
Clean up all PCI operations in mainboards based on AMD 690: amd/pistachio amd/dbm690t technexion/tim8690
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Peter Stuge peter@stuge.se
Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4647&device=ep405pc&... Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4647&device=sandpointx3... Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4647&device=briq&ve...
If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed.
If this issue is not fixed within 24h the revision should be backed out.
Best regards, coreboot automatic build system
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