BIOS shadowing

[Felix Radensky]

Hi, folks

I'm trying to implement BIOS shadowing for Intel 440bx
chipset in freebios v1 code. Shadowing of 0xf0000-0xfffff is
controlled by PAM0 register in the north bridge. Here's
the code.

#define PAM0 0x59
#define CONFIG_CMD(bus, devfn, where)   (0x80000000 | (bus << 16) |
(devfn << 8) | (where & ~3))

extern void cache_disable(void);
extern void cache_enable(void);

extern unsigned long _text, _erodata;
unsigned long *bios_start = &_text;
unsigned long *bios_end = &_erodata;

/* Shadow BIOS text and rodata into RAM */
static inline void bios_shadow(void)
{
        cache_disable();

/* Set attributes for 0xf0000-0xfffff to write only */
        outl(CONFIG_CMD(0, PCI_DEVFN(0, 0), PAM0), PCI_CONF_REG_INDEX);
        outb(0x20, PCI_CONF_REG_DATA + (PAM0 & 3));

while (bios_start <= bios_end) {
                volatile unsigned long tmp;
                tmp = *bios_start;
                *bios_start++ = tmp;
        }

/* Set attributes for 0xf0000-0xfffff to read only */
        outl(CONFIG_CMD(0, PCI_DEVFN(0, 0), PAM0), PCI_CONF_REG_INDEX);
        outb(0x10, PCI_CONF_REG_DATA + (PAM0 & 3));

cache_enable();
}

This code works for me, however I have a question. When this code is
executed, 0xf0000-0xfffff is configured as uncacheable via the
corresponding MTRRs. However disabling of caching is essential  for
this code to work, and I  don't understand why.
Can someone please shed a light on this ?

Thanks a lot.

Felix.