Why enable cache in amd_early_mtrr_init?
That causes CPU sleep 5s again.
After get rid of that, the new auto.c stage still cost more 1s than the code two weeks ago.
Regards
YH
-----Original Message----- From: YhLu Sent: Tuesday, October 19, 2004 6:30 PM To: ebiederman@lnxi.com Cc: Li-Ta Lo; 'Ronald G. Minnich'; 'LinuxBIOS' Subject: RE: FYI: Merge in progress...
Suggest you to add two options 1. premem 64 bit support? PCI_MEM_PREF_64BIT_SUPPORT 2. pci mmio optimizing? PCI_MEM_BASE_OPTIMIZATION
Regards
YH
-----Original Message----- From: ebiederman@lnxi.com [mailto:ebiederman@lnxi.com] Sent: Tuesday, October 19, 2004 4:37 PM To: YhLu Cc: Li-Ta Lo; 'ebiederman@lnxi.com'; 'Ronald G. Minnich'; 'LinuxBIOS' Subject: Re: FYI: Merge in progress...
YhLu YhLu@tyan.com writes:
Find out the problem, should be typo error.
/* Now place the memory as high up as it will go */ mem2->base = resource_max(mem2); mem1->limit = mem2->base - 1; mem1->base = resource_max(mem2);
------> /* Now place the memory as high up as it will go */ mem2->base = resource_max(mem2); mem1->limit = mem2->base - 1; mem1->base = resource_max(mem1);
regards
Thanks. That was a definite blind spot, on my side.
I have now committed the fix.
Eric
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YhLu YhLu@tyan.com writes:
Why enable cache in amd_early_mtrr_init?
Usually that is a speed up. I think all I changed was using the C implementation. Previously the assembly was called from Config.lb.
That causes CPU sleep 5s again.
That is peculiar.
After get rid of that, the new auto.c stage still cost more 1s than the code two weeks ago.
Hmm.
This is certainly worth fixing. And it tends to explain why I have not yet seen the 5s speed up.
Eric