update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
What was dongle.py in top makefile?
On 8/10/10 5:06 PM, ali hagigat wrote:
update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
What was dongle.py in top makefile?
It's the program controlling this: http://www.coreboot.org/FlexyICE
Unless you have one of those you don't need to worry.
Stefan
Am 10.08.2010 17:06, schrieb ali hagigat:
update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
What was dongle.py in top makefile?
dongle.py is a utility to control the Artec FlexyICE dongle (hence the name of the tool). The dongle serves as a PLCC emulator, with cuts down on roundtrip times for developers that use it.
See http://www.coreboot.org/Artecgroup_programmable_LPC_dongle
Given that you manage to ask only about the less important parts of the tree, I guess I can be happy to assume that you have no issues with the basic operation of the tree.
Patrick
My main questions are not answered!
Starting from top makefile, what is first rule that is executed? How this makefile causes other makefiles inside the subdirectories are called? Please mention the line which does this.
Thank you.
On Tue, Aug 10, 2010 at 7:41 PM, Patrick Georgi patrick@georgi-clan.dewrote:
Am 10.08.2010 17:06, schrieb ali hagigat:
update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
What was dongle.py in top makefile?
dongle.py is a utility to control the Artec FlexyICE dongle (hence the name of the tool). The dongle serves as a PLCC emulator, with cuts down on roundtrip times for developers that use it.
See http://www.coreboot.org/Artecgroup_programmable_LPC_dongle
Given that you manage to ask only about the less important parts of the tree, I guess I can be happy to assume that you have no issues with the basic operation of the tree.
Patrick
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
ali hagigat wrote:
Starting from top makefile, what is first rule that is executed?
I think this depends on which target you are building. Why do you ask?
How this makefile causes other makefiles inside the subdirectories are called? Please mention the line which does this.
It's not one line. coreboot uses a Makefile scheme which was inspired by the Linux kernel Makefile scheme and rules. By studying the Makefile rules in coreboot you'll see that it's not as simple as you may expect.
In any case, a starting point for studying the Makefile rules might be the line starting with:
includemakefiles=
in the top level Makefile.
//Peter
do a make and watch what gets executed. There's no substitute for observation and interaction with the tool.
ron
On Tue, Aug 10, 2010 at 8:43 AM, ali hagigat hagigatali@gmail.com wrote:
My main questions are not answered!
Starting from top makefile, what is first rule that is executed? How this makefile causes other makefiles inside the subdirectories are called? Please mention the line which does this.
There's no recursive make.
ron
On Tue, Aug 10, 2010 at 9:03 AM, ron minnich rminnich@gmail.com wrote:
On Tue, Aug 10, 2010 at 8:43 AM, ali hagigat hagigatali@gmail.com wrote:
My main questions are not answered!
Starting from top makefile, what is first rule that is executed? How this makefile causes other makefiles inside the subdirectories are called? Please mention the line which does this.
There's no recursive make.
if only ;-)
http://miller.emu.id.au/pmiller/books/rmch/
http://miller.emu.id.au/pmiller/books/rmch/
Am 10.08.2010 22:40, schrieb David Hendricks:
There's no recursive make.
if only ;-)
The only recursive make in coreboot is when you use the scanbuild feature. In which case the toplevel Makefile calls itself, wrapped in scan-build. Everything else is iterative inclusion of makefile fragments (manually tail-optimized recursion, if you wish)
Our main bottleneck right now is lots and lots of directory accesses, for all the files involved. Our main issue with the dependency graph is that some dependencies are hard to represent sanely in make.
Patrick
On 8/10/10 5:43 PM, ali hagigat wrote:
My main questions are not answered!
Maybe people think you should ask general GNU make questions to the GNU make developers or read the GNU make documentation.
Starting from top makefile, what is first rule that is executed?
The first one in the top level Makefile. That's the same for all "make" based projects.
How this makefile causes other makefiles inside the subdirectories are called? Please mention the line which does this.
See lines 185 - 211 in the top level makefile