Re: [coreboot] AMG G-series - Steppe eagle - PCI IRQ Routing to 8259 PIC

[Rudolf Marek]

Hi Abhishek,

Please can you check if you programmed the ELCR registers 0x4d0/0x4d1
to level for PCI registers?

In other words, you should set bits to 1 to corresponding IRQ to be level
triggered. Eg. for IRQ 5, you need to write 1 to bit5 to 8bit I/O port 0x4d0 For
IRQ 9, you need to program bit 1 of 0x4d1

You can also check the PCI status register (reg  of Ethernet device, there is
"interrupt pending" bit, to verify that the device actually tries to trigger the
IRQ. Also, you can check if INTX disable is not set in PCI register by accident.

lspci -vvv
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort-
> SERR- <PERR- INTx-

You should see  DisINTx- and INTx+ (if interrupt is pending).

The local APIC has also individual vector interrupt disable bits (but you say
local apic is disabled, normally for te local APIC should have programmed EXTINT
mode on LINT0, or virtual wire in IOAPIC)

Has this platform more than 1 IOAPIC, or just IOAPIC in SB?

Thanks
Rudolf

AMG G-series - Steppe eagle - PCI IRQ Routing to 8259 PIC

[Abhishek Chaudhary]

Rudolf,

Thank you so much for your response.

Its working now. The problem was that i was writting the ELCR register as a
16bit I/O register, because it is listed as one 16 bit register in BKDG
@0x4D0. When i wrote the slave IRQs to 0x4D1, it worked.

Thank you once again for your time.

Thanks.
Abhishek.

On Mon, Nov 6, 2017 at 1:38 AM, Rudolf Marek  wrote:
> Hi Abhishek,
>
> Please can you check if you programmed the ELCR registers 0x4d0/0x4d1
> to level for PCI registers?
>
> In other words, you should set bits to 1 to corresponding IRQ to be level
> triggered. Eg. for IRQ 5, you need to write 1 to bit5 to 8bit I/O port
> 0x4d0 For
> IRQ 9, you need to program bit 1 of 0x4d1
>
> You can also check the PCI status register (reg  of Ethernet device, there
> is
> "interrupt pending" bit, to verify that the device actually tries to
> trigger the
> IRQ. Also, you can check if INTX disable is not set in PCI register by
> accident.
>
> lspci -vvv
> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping-
> SERR- FastB2B- DisINTx+
> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
> <MAbort-
> > SERR- <PERR- INTx-
>
> You should see  DisINTx- and INTx+ (if interrupt is pending).
>
> The local APIC has also individual vector interrupt disable bits (but you
> say
> local apic is disabled, normally for te local APIC should have programmed
> EXTINT
> mode on LINT0, or virtual wire in IOAPIC)
>
> Has this platform more than 1 IOAPIC, or just IOAPIC in SB?
>
> Thanks
> Rudolf