Author: rminnich Date: 2008-11-13 18:42:52 +0100 (Thu, 13 Nov 2008) New Revision: 1017
Added: coreboot-v3/southbridge/intel/i82801gx/libsmbus.c coreboot-v3/southbridge/intel/i82801gx/usb_ehci.dts Modified: coreboot-v3/mainboard/kontron/986lcd-m/Makefile coreboot-v3/mainboard/kontron/986lcd-m/dts coreboot-v3/southbridge/intel/i82801gx/Makefile Log: fix compile errors and Ron's Makefile mistake. Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: coreboot-v3/mainboard/kontron/986lcd-m/Makefile =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-11-13 17:14:16 UTC (rev 1016) +++ coreboot-v3/mainboard/kontron/986lcd-m/Makefile 2008-11-13 17:42:52 UTC (rev 1017) @@ -28,18 +28,7 @@ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/intel/i945/raminit.c \
-STAGE2_CHIPSET_SRC=\ - $(src)/southbridge/intel/i82801gx/ac97.c \ - $(src)/southbridge/intel/i82801gx/lpc.c \ - $(src)/southbridge/intel/i82801gx/nic.c \ - $(src)/southbridge/intel/i82801gx/pci.c \ - $(src)/southbridge/intel/i82801gx/pcie.c \ - $(src)/southbridge/intel/i82801gx/sata.c \ - $(src)/southbridge/intel/i82801gx/smbus.c \ - $(src)/southbridge/intel/i82801gx/usb_ehci.c \ - $(src)/southbridge/intel/i82801gx/usb.c \ - $(src)/southbridge/intel/i82801gx/watchdog.c -# $(src)/southbridge/intel/i82801gx/libsmbus.c \ +STAGE2_CHIPSET_SRC=
STAGE2_MAINBOARD_SRC =
Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-13 17:14:16 UTC (rev 1016) +++ coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-13 17:42:52 UTC (rev 1017) @@ -181,7 +181,10 @@ pci@1f,0{/* which ich? */ /config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts"); }; - pci@1f,2{ + pci@1f,1{ + /config/("southbridge/intel/i82801gx/ide.dts"); + }; + pci@1f,2{ /config/("southbridge/intel/i82801gx/sata.dts"); }; pci@1f,3{
Modified: coreboot-v3/southbridge/intel/i82801gx/Makefile =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-13 17:14:16 UTC (rev 1016) +++ coreboot-v3/southbridge/intel/i82801gx/Makefile 2008-11-13 17:42:52 UTC (rev 1017) @@ -24,9 +24,20 @@ STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/i82801gx.c
STAGE2_CHIPSET_SRC += \ - + $(src)/southbridge/intel/i82801gx/ac97.c \ + $(src)/southbridge/intel/i82801gx/lpc.c \ + $(src)/southbridge/intel/i82801gx/nic.c \ + $(src)/southbridge/intel/i82801gx/pci.c \ + $(src)/southbridge/intel/i82801gx/pcie.c \ + $(src)/southbridge/intel/i82801gx/sata.c \ + $(src)/southbridge/intel/i82801gx/smbus.c \ + $(src)/southbridge/intel/i82801gx/usb_ehci.c \ + $(src)/southbridge/intel/i82801gx/usb.c \ + $(src)/southbridge/intel/i82801gx/watchdog.c \ + $(src)/southbridge/intel/i82801gx/libsmbus.c \ + STAGE0_CHIPSET_SRC += \ $(src)/southbridge/intel/i82801gx/stage1_smbus.c \ -# $(src)/southbridge/intel/i82801gx/libsmbus.c \ + $(src)/southbridge/intel/i82801gx/libsmbus.c \
endif
Added: coreboot-v3/southbridge/intel/i82801gx/libsmbus.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/libsmbus.c (rev 0) +++ coreboot-v3/southbridge/intel/i82801gx/libsmbus.c 2008-11-13 17:42:52 UTC (rev 1017) @@ -0,0 +1,193 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu yinghailu@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci.h> +#include <statictree.h> +#include <config.h> +#include <io.h> +#include <device/smbus_def.h> +#include "i82801gx.h" + +/* this is very chipset-specific. */ +#define SMBUS_TIMEOUT (100*1000*10) +/* These are common functions used in stage 1 and stage2 */ +void smbus_delay(void) +{ + inb(0x80); +} + +int smbus_wait_until_ready(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while (byte & 1); + return loops ? 0 : -1; +} + +int smbus_wait_until_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); + return loops ? 0 : -1; +} + +int smbus_wait_until_blk_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & (1 << 7)) == 0); + return loops ? 0 : -1; +} + +int do_smbus_read_byte(unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* Set the device I'm talking to */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (SMBUS_IO_BASE + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} + +/* This function is neither used nor tested by me (Corey Osgood), the author +(Yinghai) probably tested/used it on i82801er */ +int do_smbus_write_block(u16 device, unsigned int length, unsigned int cmd, + unsigned data1, unsigned data2) +{ + u8 byte; + u8 stat; + int i; + + printk(BIOS_ERR, "Untested smbus_write_block called\n"); + /* Clear the PM timeout flags, SECOND_TO_STS */ + outw(inw(0x0400 + 0x66), 0x0400 + 0x66); + + if (smbus_wait_until_ready() < 0) { + return -2; + } + + /* Setup transaction */ + /* Obtain ownership */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + for (stat = 0; (stat & 0x40) == 0;) { + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + /* Clear the done bit */ + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); + + /* Set the command address */ + outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + + /* Set the block length */ + outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Try sending out the first byte of data here */ + byte = (data1 >> (0)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + /* Issue a block write command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, + SMBUS_IO_BASE + SMBHSTCTL); + + for (i = 0; i < length; i++) { + + /* Poll for transaction completion */ + if (smbus_wait_until_blk_done() < 0) { + return -3; + } + + /* Load the next byte */ + if (i > 3) + byte = (data2 >> (i % 4)) & 0x0ff; + else + byte = (data1 >> (i)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + + /* Clear the done bit */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + + printk(BIOS_DEBUG, "SMBUS Block complete\n"); + + return 0; +}
Added: coreboot-v3/southbridge/intel/i82801gx/usb_ehci.dts =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/usb_ehci.dts (rev 0) +++ coreboot-v3/southbridge/intel/i82801gx/usb_ehci.dts 2008-11-13 17:42:52 UTC (rev 1017) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich rminnich@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "i82801gx_usb_ehci"; +};
-
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