[PATCH] flashrom: Trim default ICH SPI delay from 1000 to 10 microseconds

[Carl-Daniel Hailfinger]

Trim default ICH SPI delay from 1000 to 10 microseconds. Since many
commands take around 10 microseconds to complete, it is totally
pointless to wait for 1000 microseconds before checking the status again.

This patch is tested and reduced write time on ICH7 with SST25VF080B
from over one hour to 62 seconds.

Thanks to Ali Nadalizadeh for testing!

Signed-off-by: Carl-Daniel Hailfinger

Index: flashrom-ichspi_delay/ichspi.c
===================================================================
--- flashrom-ichspi_delay/ichspi.c	(Revision 471)
+++ flashrom-ichspi_delay/ichspi.c	(Arbeitskopie)
@@ -458,9 +458,9 @@
    REGWRITE16(ICH7_REG_SPIC, temp16);

/* wait for cycle complete */
-	timeout = 1000 * 60;	// 60s is a looong timeout.
+	timeout = 100 * 1000 * 60;	// 60s is a looong timeout.
    while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
-		myusec_delay(1000);
+		myusec_delay(10);
    }
    if (!timeout) {
    	printf_debug("timeout\n");
@@ -575,9 +575,9 @@
    REGWRITE32(ICH9_REG_SSFS, temp32);

/*wait for cycle complete */
-	timeout = 1000 * 60;	// 60s is a looong timeout.
+	timeout = 100 * 1000 * 60;	// 60s is a looong timeout.
    while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
-		myusec_delay(1000);
+		myusec_delay(10);
    }
    if (!timeout) {
    	printf_debug("timeout\n");

[PATCH] flashrom: Trim default ICH SPI delay from 1000 to 10 microseconds

[Myles Watson]

On Thu, May 7, 2009 at 6:45 PM, Carl-Daniel Hailfinger
 wrote:
> Trim default ICH SPI delay from 1000 to 10 microseconds. Since many
> commands take around 10 microseconds to complete, it is totally
> pointless to wait for 1000 microseconds before checking the status again.
>
> This patch is tested and reduced write time on ICH7 with SST25VF080B
> from over one hour to 62 seconds.
>
> Thanks to Ali Nadalizadeh for testing!
>
> Signed-off-by: Carl-Daniel Hailfinger

Acked-by: Myles Watson

I like the 1 hour to 62 seconds.

Thanks,
Myles
> Index: flashrom-ichspi_delay/ichspi.c
>
> --- flashrom-ichspi_delay/ichspi.c      (Revision 471)
> +++ flashrom-ichspi_delay/ichspi.c      (Arbeitskopie)
> @@ -458,9 +458,9 @@
>        REGWRITE16(ICH7_REG_SPIC, temp16);
>
> /* wait for cycle complete */
> timeout = 1000 * 60;    // 60s is a looong timeout.
> timeout = 100 * 1000 * 60;      // 60s is a looong timeout.
>
> while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
> myusec_delay(1000);
> myusec_delay(10);
>
> }
>        if (!timeout) {
>                printf_debug("timeout\n");
> @@ -575,9 +575,9 @@
>        REGWRITE32(ICH9_REG_SSFS, temp32);
>
> /*wait for cycle complete */
> timeout = 1000 * 60;    // 60s is a looong timeout.
> timeout = 100 * 1000 * 60;      // 60s is a looong timeout.
>
> while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
> myusec_delay(1000);
> myusec_delay(10);
>
> }
>        if (!timeout) {
>                printf_debug("timeout\n");
> Index: flashrom-ichspi_delay/ichspi.c
>
> --- flashrom-ichspi_delay/ichspi.c      (Revision 471)
> +++ flashrom-ichspi_delay/ichspi.c      (Arbeitskopie)
> @@ -458,9 +458,9 @@
>        REGWRITE16(ICH7_REG_SPIC, temp16);
>
> /* wait for cycle complete */
> timeout = 1000 * 60;    // 60s is a looong timeout.
> timeout = 100 * 1000 * 60;      // 60s is a looong timeout.
>
> while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
> myusec_delay(1000);
> myusec_delay(10);
>
> }
>        if (!timeout) {
>                printf_debug("timeout\n");
> @@ -575,9 +575,9 @@
>        REGWRITE32(ICH9_REG_SSFS, temp32);
>
> /*wait for cycle complete */
> timeout = 1000 * 60;    // 60s is a looong timeout.
> timeout = 100 * 1000 * 60;      // 60s is a looong timeout.
>
> while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
> myusec_delay(1000);
> myusec_delay(10);
>
> }
>        if (!timeout) {
>                printf_debug("timeout\n");

[PATCH] flashrom: Trim default ICH SPI delay from 1000 to 10 microseconds

[Carl-Daniel Hailfinger]

On 09.05.2009 05:42, Myles Watson wrote:
> On Thu, May 7, 2009 at 6:45 PM, Carl-Daniel Hailfinger
>  wrote:
> > Trim default ICH SPI delay from 1000 to 10 microseconds. Since many
> > commands take around 10 microseconds to complete, it is totally
> > pointless to wait for 1000 microseconds before checking the status again.
> >
> > This patch is tested and reduced write time on ICH7 with SST25VF080B
> > from over one hour to 62 seconds.
> >
> > Thanks to Ali Nadalizadeh for testing!
> >
> > Signed-off-by: Carl-Daniel Hailfinger
>
> Acked-by: Myles Watson
>
> I like the 1 hour to 62 seconds.

Thanks, committed in r487.

Regards,
Carl-Daniel