RFC: automatic mptable creation - coreboot

25 Jun 2012


      Hi coreboot folks,
i've just pushed the following changes for discussion:
http://review.coreboot.org/#/c/1137/
http://review.coreboot.org/#/c/1138/
Those changes add support for creating the MPTABLE during runtime,
which resolves one of the most painful tasks in the past during
porting a new board.
Basically the first patch adds a generic IOAPIC driver, which
can be added to the devicetree, and holds the generic configuration
data, and does all the IOAPIC initialization. An example entry looks
like this (two entries, as mny X7DB8 has two IOAPICs):
chip drivers/generic/ioapic
                        register "irq_on_fsb" = "1"
                        register "base" = "0xfec00000"
                        register "have_isa_interrupts" = "1"
                        register "enable_virtual_wire" = "1"
                        device ioapic 8 on end
                end
                chip drivers/generic/ioapic
                        register "irq_on_fsb" = "1"
                        register "base" = "0xfec80000"
                        device ioapic 9 on end
                end
I think the entries are pretty self-explaining - the
'have_isa_interrupts' tells the mptable code for which IOAPIC to
generate the ISA interrupts.
The second patch adds support for the 'ioapic_irq' keyword, and the main
mptable stuff. The ioapic_irq has the following syntax:
ioapic_irq APICID PCI-INT-PIN IOAPIC-IRQ-PIN
PCI-INT-PIN is currently an integer, where 0 stands for INTA, 1 for INTB
and so on. Patrick Georgi suggested to change that to A/B/C/D, which i
might do later. For non onboard device the mptable code currently
searches for ioapic entries of the parents, and writes the appropriate
IRQ entries.
With that patch, a devicetree could look like this:
device pci 02.0 on # PCI Express x8 Port 2-3
        	ioapic_irq 8 0 0x10
                ioapic_irq 8 1 0x11
                ioapic_irq 8 2 0x12
                ioapic_irq 8 3 0x13
                device pci 00.0 on # PCI Express Upstream Port
                	device pci 00.0 on # PCI Express Downstream Port E1
                            device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A
                                    ioapic_irq 8 0 0x11
                                        ioapic_irq 8 1 0x10
                                        ioapic_irq 8 2 0x11
                                        ioapic_irq 8 3 0x10
                                        # PCI slot
                                        device pci 02.0 on # Adaptec U320 #1
                                            ioapic_irq 8 0 0x10
                                        end
                                        device pci 02.1 on # Adaptec U320 #2
                                                ioapic_irq 8 1 0x11
                                        end
                                end
                                device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B
                                                # PCI slot
                                end
                        end
                        device pci 02.0 on # PCI Express Port E3
                            device pci 00.0 on end # e1000 #1
                                device pci 00.1 on end # e1000 #2
                        end
                 end
                 device pci 00.3 on # PCI Express to PCI-X Bridge
                 	ioapic_irq 9 0 3
                        ioapic_irq 9 1 0
                        ioapic_irq 9 2 1
                        ioapic_irq 9 3 2
                        # PCI-X Slot
                        end
           end
I would be really happy to see people checking the patch, and especially
checking that my logic is correct. I'm also happy to hear about
improvements, bug fixes, and other ideas.
Thanks for listening,
Sven