Hi!
Please tell me where I can get the decryption of post codes that appear during Intel FSP operation? Codes such as 0x57, 0x59, 0x58, 0x62 ... I see that they appear during testing and memory tuning, but I would like to have more detailed information. Maybe someone knows the number of the Intel document to download?
Regards, Dmitry
Hi Dmitry,
Which FSP version do you have? 1.0, 1.1, 2.0, 2.1?
Typically post codes are described in the integration guides for FSP. You can find one for your particular FSP and platform here: https://github.com/IntelFsp/FSP
For example https://github.com/IntelFsp/FSP/blob/master/KabylakeFspBinPkg/Docs/Kabylake_...
section umber 5: FSP POSTCODE.
Regards, Michał
On 12.11.2019 20:18, dponamorev@gmail.com wrote:
Hi!
Please tell me where I can get the decryption of post codes that appear during Intel FSP operation? Codes such as 0x57, 0x59, 0x58, 0x62 ... I see that they appear during testing and memory tuning, but I would like to have more detailed information. Maybe someone knows the number of the Intel document to download?
Regards, Dmitry _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
I use FSP version 2.0 for Intel Denverton_ns. Unfortunately in the directory for this processor the documentation does not contain information on post codes...
Hi Dmitry,
This depends on the FSP that is used. In most cases the information is in the Integration Guide.
Normally the guide can be found in the 3rdparty/fsp directory.
Best Regards, Wim Vervoorn Eltan B.V.
-----Original Message----- From: dponamorev@gmail.com [mailto:dponamorev@gmail.com] Sent: Tuesday, November 12, 2019 8:18 PM To: coreboot@coreboot.org Subject: [coreboot] Decryption of post codes that appear during Intel FSP operation?
Hi!
Please tell me where I can get the decryption of post codes that appear during Intel FSP operation? Codes such as 0x57, 0x59, 0x58, 0x62 ... I see that they appear during testing and memory tuning, but I would like to have more detailed information. Maybe someone knows the number of the Intel document to download?
Regards, Dmitry _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi Wim Vervoorn
I use FSP 2.0 for denverton_ns. Unfortunately in the directory for this processor the documentation does not contain information on post codes
Regards, Dmitry
Thank you all, I found the necessary information in the document: Aspen Cove Customer Reference Board (CRB) User Guide March 2016 Document Number: 566111, Revision: 1.0