Patch merged into coreboot/master: cc689fe Rework Sandybridge MRC cache handling

the following patch was just integrated into master:
commit cc689fe22e9e8649e31292c6ad1cad6499c34bb8
Author: Stefan Reinauer 
Date:   Thu May 10 11:31:40 2012 -0700

Rework Sandybridge MRC cache handling

- Separate Sandybridge from ChromeOS a bit
      The Sandybridge code depends on chromeos features a whole lot.
      As a first step, provide a code path to look up the MRC cache
      without depending on u-boot.

- Move mrc cache handling to separate file
      This enables us to handle the MRC cache from ramstage,
      where we can write the flash safely (eg. to update the
      cache).
      Also teach it to lookup the current MRC cache from CBMEM,
      as the original data block isn't available anymore.

After all the preparations, finally write to the SPI
    as necessary. It's a simple round robin wear levelling
    that erases the entire MRC cache region when it's full
    and starts from the beginning.

Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12
    Signed-off-by: Patrick Georgi

Build-Tested: build bot (Jenkins) at Thu May 10 21:41:27 2012, giving +1
See http://review.coreboot.org/1001 for details.

-gerrit