New subject: New board with unsupported cpu, chipset, and superIO

28 Aug 2014


      Wonderful writeup Paul, thank you. see below…
On Aug 28, 2014, at 9:59 AM, Paul Wilcox-Baker wilcoxbaker@gmail.com wrote:
...
Dear Todd,
...
It appears (from following the instructions) that I have a new board
with unsupported cpu, chipset, and superIO.
...
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core
Processor DRAM Controller (rev 06)
00:1f.0 ISA bridge: Intel Corporation HM86 Express LPC Controller (rev
05)
We are interested in a BIOS for the same processor family, but a different
PCH device.
Maybe we can work together in this effort, I did track down a longtime developer relationship I have, who did BIOS development for Xerox, and is available to get involved with coreboot.
...
...
c) If there is any coreboot developers that would be willing to contract
for hire to develop coreboot for this board?
There is a company, Sage Engineering that ports coreboot to various
processors.  We are probably going to use them.   See
http://www.se-eng.com or to ask a question use:
http://www.se-eng.com/contact/
I was referred to them yesterday, and am in contact with them, we will very likely use their expertise.
...
From what I have been able to find out you need some binary "secret sauce"
that comes from Intel.  This allows coreboot to do things like set up the
DRAM controller and video.  The problem is that Intel only lets a few
people have access to this code.
For instance, for one of the people who could get this code, they claim
the process is this simple:
http://www.coreboot.org/pipermail/coreboot/2014-July/078275.html
The above information is remarkably helpful in figuring out how to proceed! I really appreciate getting this overview.
...
...
It appears "If it is not supported by coreboot then you will have a lot
of work in front of you."
This view, is based on not having the Intel code and writing your own code
to set up the DRAM controllers.  I imagine that it would be very difficult
to write code for modern DRAM controllers, you have to read the EEPROMs
on the DIMMs to determine the DRAM size and other characteristics, then
set up the controller to match.  Finally, DDR3 (used by this processor) has a
training phase to get data accesses aligned in time.  This might be implemented
in hardware, or you might have to write code to do it.  I don't know!
The truth here is that we NEED to have a blob-free version (libreboot), so I have a lot of work ahead of me :)
...
If you get a different story about this, I would love to hear it.
Thanks, Paul
The story I’ve heard thus far is exactly as you spell it out, even though you have provided more information in certain parts.
Thanks Paul, and let me know if we can pool resources to get this to happen!
Todd.

Re: [coreboot] New board with unsupported cpu, chipset, and superIO