Hmm. I think this also is true with some Intel chipsets. Even without graphics enabled there has to be some kind of reserved memory space just below tolm (the smallest I was sucessfull with was 1MB) or filo chokes. Doesn't LB allocate a bounce buffer just before the payload starts? Is this bounce buffer just below tolm??
Thanks - Joe
yes, this bounce buffer is just below tolm with the size twice of (&_eram_seg - &_ram_seg).
I'm now having trouble with mtrr, after setting variable mtrr, data gets corrupted. If only set and enable fixed range mtrr, everything works fine except that I have to reserve extra space near the tolm or filo couldn't start. With variable mtrr not set(but enabled by earlymtrr), the linux kernel could be booted though the speed is aweful...
On Dec 26, 2007 1:58 AM, aaron lwe aaron.lwe@gmail.com wrote:
I'm now having trouble with mtrr, after setting variable mtrr, data gets corrupted.
this can be still be caused by bad dram timing. Once you start caching, cache flush to ram will be a burst. If the dram timing is not right, you will get data corruption that will not occur with caching off. I used to have this happen very frequently.
So, I still think you have a memory configuration problem.
ron