Any thing that we need to prepare?
1. dual core: cpu scan in northbridge.c or amd_sibling_init... 2. Cache as RAM.... 3. ACPI: how to create DSDT ( Config.lb + scan to produce AMI directly?) Only support _PRT at first step? 4. ACPI: SRAT scan pci conf? 5. Open Firmware support in Kernel for i386 and x86_64 6. OpenEFI or FreeEFI as payload for LinuxBIOS....? 7. USB ROM eumluator in Linux.... 8. Serverworks chipset: Who and how? 9. CK804 support etc...., Steven from Bench? 10. K8 E0 memhole support in raminit.c or northbridge.c?
Regards
Yinghai Lu
"Lu, Yinghai" yinghai.lu@amd.com writes:
Any thing that we need to prepare?
- dual core: cpu scan in northbridge.c or amd_sibling_init...
- Cache as RAM....
- ACPI: how to create DSDT ( Config.lb + scan to produce AMI directly?)
Only support _PRT at first step? 4. ACPI: SRAT scan pci conf? 5. Open Firmware support in Kernel for i386 and x86_64 6. OpenEFI or FreeEFI as payload for LinuxBIOS....?
Before we generate ACPI or anything else we need to move the relevant information into the internal device tree.
- USB ROM eumluator in Linux....
- Serverworks chipset: Who and how?
- CK804 support etc...., Steven from Bench?
- K8 E0 memhole support in raminit.c or northbridge.c?
Worth discussing. But this has always been very successfully handled in northbridge.c on Intel chipsets and it works equally well on AMD chipsets. The implementation should be in patch 4/16.
11. LinuxBIOS Maintenance. How can we do better?
Eric
On 9/6/05, Eric W. Biederman ebiederman@lnxi.com wrote:
"Lu, Yinghai" yinghai.lu@amd.com writes:
Any thing that we need to prepare?
- dual core: cpu scan in northbridge.c or amd_sibling_init...
- Cache as RAM....
- ACPI: how to create DSDT ( Config.lb http://Config.lb + scan to
produce AMI directly?)
Only support _PRT at first step? 4. ACPI: SRAT scan pci conf? 5. Open Firmware support in Kernel for i386 and x86_64 6. OpenEFI or FreeEFI as payload for LinuxBIOS....?
Before we generate ACPI or anything else we need to move the relevant information into the internal device tree.
YH: Good point, But I worry that we make LinuxBIOS more complicated.
- USB ROM eumluator in Linux....
- Serverworks chipset: Who and how?
- CK804 support etc...., Steven from Bench?
- K8 E0 memhole support in raminit.c or northbridge.c?
Worth discussing. But this has always been very successfully handled in northbridge.c on Intel chipsets and it works equally well on AMD chipsets. The implementation should be in patch 4/16.
YH: That is good feature. Please consider to add several option in CMOS for that 0: auto 1: 512M, 2:1G, 3: 2G----------> need 2 bits
11. LinuxBIOS Maintenance. How can we do better?
YH: I agree we need a. one process for coordination such as chipset support. and share source code before publish ( three parties NDA?) c. one process for source code release control..., stable tag... b. move back the list and public source tree to US.
Eric
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* yhlu yinghailu@gmail.com [050907 06:04]:
Before we generate ACPI or anything else we need to move the relevant information into the internal device tree.
YH: Good point, But I worry that we make LinuxBIOS more complicated.
No, the information has to be reorganized. Currently pirq and mptables have to be hand crafted, and this is the complicated thing. Instead the abstract information should be put to the configuration filess, if it can not be probed.
11. LinuxBIOS Maintenance. How can we do better?
YH: I agree we need
b. move back the list and public source tree to US.
what's wrong with the status quo?
Stefan
Stefan Reinauer stepan@openbios.org writes:
- yhlu yinghailu@gmail.com [050907 06:04]:
11. LinuxBIOS Maintenance. How can we do better?
YH: I agree we need
b. move back the list and public source tree to US.
what's wrong with the status quo?
I don't see a problem with the servers right now.
Does anyone have any specific problems with the servers?
Eric