On 9/6/05, Eric W. Biederman <ebiederman@lnxi.com> wrote:
"Lu, Yinghai" <yinghai.lu@amd.com> writes:
> Any thing that we need to prepare?
>
> 1. dual core: cpu scan in northbridge.c or amd_sibling_init...
> 2. Cache as RAM....
> 3. ACPI: how to create DSDT ( Config.lb + scan to produce AMI directly?)
> Only support _PRT at first step?
> 4. ACPI: SRAT scan pci conf?
> 5. Open Firmware support in Kernel for i386 and x86_64
> 6. OpenEFI or FreeEFI as payload for LinuxBIOS....?
Before we generate ACPI or anything else we need to move the relevant information
into the internal device tree.
YH: Good point, But I worry that we make LinuxBIOS more complicated.
> 7. USB ROM eumluator in Linux....
> 8. Serverworks chipset: Who and how?
> 9. CK804 support etc...., Steven from Bench?
> 10. K8 E0 memhole support in raminit.c or northbridge.c?
Worth discussing. But this has always been very successfully handled
in northbridge.c on Intel chipsets and it works equally well on
AMD chipsets. The implementation should be in patch 4/16.
YH: That is good feature. Please consider to add several option in CMOS for that
0: auto 1: 512M, 2:1G, 3: 2G----------> need 2 bits
11. LinuxBIOS Maintenance. How can we do better?
YH: I agree we need
a. one process for coordination such as chipset support. and share
source code before publish ( three parties NDA?)
c. one process for source code release control..., stable tag...
b. move back the list and public source tree to US.
Eric
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