Patch set updated for coreboot: 0b63aff AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU

[Siyuan Wang]

Siyuan Wang ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1659

-gerrit

commit 0b63aff4f8a25c84e47d8e93c7c5dd33b8d55a69
Author: Siyuan Wang 
Date:   Wed Oct 31 15:39:51 2012 +0800

AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU

Each G34 socket has two node. Previous lapic algorithm is written for
    the CPU which has one node per socket. I test the code on h8qgi with
    4 family 15 CPUs(8 cores per CPU). The topology is:
    socket 0 --> Node 0, Node 1
    socket 2 --> Node 2, Node 3
    socket 1 --> Node 4, Node 5
    socket 3 --> Node 6, Node 7
    Each node has 4 cores.
    I change the code according to this topology.

Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855
    Signed-off-by: Siyuan Wang 
    Signed-off-by: Siyuan Wang 
---
 src/northbridge/amd/agesa/family15/northbridge.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 12a211f..78986e4 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -1068,7 +1068,11 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
    			lapicid_start = (lapicid_start + 1) * core_max;
    			printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
    		}
-			u32 apic_id = (i * core_max) + j + lapicid_start;
+#if CONFIG_CPU_AMD_SOCKET_G34
+			u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0);
+#else
+			u32 apic_id = (i  * core_max) + j + lapicid_start;
+#endif
    		printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
    				i, j, apic_id);