Hi,
I include log from coreboot startup on EPIA MII with 1.2GHz C3 processor. First of all it fails to run my FILO payload, second, I noticed it may fail on RAM check-up, it sees only 16MB out of 256 or 512 (tried both) Furthermore, I have to wait about 10 sec form power cycle for coreboot to send anything through serial line. Any ideas?
Thanks in advance.
Here's the log:
coreboot-2.0.0.0-Fallback Sat Feb 16 00:26:20 CST 2008 starting... In auto.c:main() Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks 01 Total Memory (*16 Mb) 10 CAS Supported 2 2.5 3 Cycle time at CL X (nS)50 Cycle time at CL X-0.5 (nS)60 Cycle time at CL X-1 (nS)75 Starting at CAS 3 We can do CAS 2.5 We can do CAS 2 tRP 3c tRCD 3c tRAS 28 Low Bond 09 High Bonddc Setting DQS delay95vt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 10 10 10 10 00 00 60:02 ff 00 30 52 32 01 20 42 2d 43 58 00 44 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 10 00 80:0f 6c 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 80 00 00 00 86 00 00 04 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00 AGP Doing MTRR init. Leaving auto.c:main() Copying coreboot to RAM. Jumping to coreboot. coreboot-2.0.0.0-Fallback Sat Feb 16 00:26:20 CST 2008 booting... clocks_per_usec: 2358 Enumerating buses... Finding PCI configuration type. Disabling static device: PCI: 00:10.3 done Allocating resources... Reading resources... Done reading resources. Setting resources... Done setting resources. Done allocating resources. Enabling resources... done. Initializing devices... Initializing CPU #0 Enabling cache Disabling local apic...done. CPU #0 Initialized pci_routing_fixup: dev is 000103b8 setting firewire setting usb setting vt8235 setting ethernet setting vga setting pci slot setting cardbus slot setting riser slot Enabling VIA IDE. ide_init: enabling compatibility IDE addresses BIOSINT: Unsupport int #0x10 Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... done. ACPI: Writing ACPI tables at f0400... ACPI: done.
Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3
Can not load ELF Image.
Hi Jacek,
On Wed, Feb 20, 2008 at 08:00:32PM -0600, Jacek Chruscik wrote:
I include log from coreboot startup on EPIA MII with 1.2GHz C3 processor.
This board should work just fine.
First of all it fails to run my FILO payload, second, I noticed it may fail on RAM check-up, it sees only 16MB out of 256 or 512 (tried both)
No, it does actually see all your RAM. More below.
Furthermore, I have to wait about 10 sec form power cycle for coreboot to send anything through serial line.
This should not happen. What kind of power supply are you using and how do you power on the board when starting coreboot?
Bank 0 (*16 Mb) 10 No Physical Banks 01 Total Memory (*16 Mb) 10
One (01) bank is found, bank 0, which has 16 (10) * 16MB = 256MB.
Note that the two-digit value last on each line here is hex but is missing a leading 0x. :\
Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3
Can not load ELF Image.
Could you send us the output from your coreboot make?
//Peter
Hi all,
I actually managed to fix the problem with loading elf image, it was faulty filo, but I still have about 10sec delay from power cycle before coreboot starts logging. I use regular PS, and original BIOS starts up immediately. I use regular power switch now, but it will be ACPI signal in the future.
So actually my original BIOS proceeds quicker than my current coreboot :(
Thanks for explaining that memory part of the log, now it makes perfect sense.
One more question, or idea; is it going to be worthwhile to modify scripts (and Config.lb options) to have ability to merge VideoBIOS (optionally) into rom image?
... and another one; Config.lb has ROM_SIZE , and ROM_SECTION_SIZE variables. I noticed that these 2 cannot have the same value (compilation fails saying "Integer constant too large" - division by zero?), but there are cases when I need to have both of them the same (single section in the rom image). Is it a bug?
I'm new to this project, thus my questions are popping, but I didn't find my answers anywhere else.
Thanks
Hi Jacek,
On Wed, Feb 20, 2008 at 08:00:32PM -0600, Jacek Chruscik wrote:
I include log from coreboot startup on EPIA MII with 1.2GHz C3 processor.
This board should work just fine.
First of all it fails to run my FILO payload, second, I noticed it may fail on RAM check-up, it sees only 16MB out of 256 or 512 (tried both)
No, it does actually see all your RAM. More below.
Furthermore, I have to wait about 10 sec form power cycle for coreboot to send anything through serial line.
This should not happen. What kind of power supply are you using and how do you power on the board when starting coreboot?
Bank 0 (*16 Mb) 10 No Physical Banks 01 Total Memory (*16 Mb) 10
One (01) bank is found, bank 0, which has 16 (10) * 16MB = 256MB.
Note that the two-digit value last on each line here is hex but is missing a leading 0x. :\
Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3
Can not load ELF Image.
Could you send us the output from your coreboot make?
//Peter
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Jacek Chruscik -
mercury＠wirebros.com
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Peter Stuge