Eric,
Is the below change intended? EPIA has problem with current CVS (resets when setting var mtrr), and it worked again when I reversed this change. According to the Intel System Programming Manual for PIII, bits 36-63 are reserved, and apparently C3 doesn't like it to be set.
black:~/src/freebios2/src/cpu/p6$ cvs diff -u -r1.4 -r1.5 mtrr.c Index: mtrr.c =================================================================== RCS file: /cvsroot/freebios/freebios2/src/cpu/p6/mtrr.c,v retrieving revision 1.4 retrieving revision 1.5 diff -u -r1.4 -r1.5 --- mtrr.c 19 Jul 2003 04:28:21 -0000 1.4 +++ mtrr.c 11 Oct 2003 06:20:17 -0000 1.5 @@ -92,7 +92,7 @@ base.lo = basek << 10;
if (sizek < 4*1024*1024) { - mask.hi = 0x0F; + mask.hi = 0x0FF; mask.lo = ~((sizek << 10) -1); } else {
SONE Takeshi ts1@tsn.or.jp writes:
Eric,
Is the below change intended?
Yes. But I put it in when Opteron was the only x86 cpu in the tree and figured I would revisit later when we started supporting other cpus.
EPIA has problem with current CVS (resets when setting var mtrr), and it worked again when I reversed this change. According to the Intel System Programming Manual for PIII, bits 36-63 are reserved, and apparently C3 doesn't like it to be set.
Ok. Then this needs to be fixed. I am wondering how we code this cleanly.
Eric
On Sat, Oct 18, 2003 at 06:37:55PM -0600, Eric W. Biederman wrote:
EPIA has problem with current CVS (resets when setting var mtrr), and it worked again when I reversed this change. According to the Intel System Programming Manual for PIII, bits 36-63 are reserved, and apparently C3 doesn't like it to be set.
Ok. Then this needs to be fixed. I am wondering how we code this cleanly.
I don't know if this is clean but it should be ok for both K8 and others. Tested on C3.
On Mon, 20 Oct 2003, SONE Takeshi wrote:
I don't know if this is clean but it should be ok for both K8 and others. Tested on C3.
committed, take a look and test if you can.
ron
On Mon, Oct 20, 2003 at 01:47:20PM -0600, ron minnich wrote:
On Mon, 20 Oct 2003, SONE Takeshi wrote:
I don't know if this is clean but it should be ok for both K8 and others. Tested on C3.
committed, take a look and test if you can.
It's fine for me but it should really be verified by people with K8.
On 18 Oct 2003, Eric W. Biederman wrote:
EPIA has problem with current CVS (resets when setting var mtrr), and it worked again when I reversed this change. According to the Intel System Programming Manual for PIII, bits 36-63 are reserved, and apparently C3 doesn't like it to be set.
Ok. Then this needs to be fixed. I am wondering how we code this cleanly.
I don't see much of an issue. The code in question sets bits that are reserved on just about any pentium-compatible CPU, and it should not. So we don't set those bits.
ron
On Mon, Oct 20, 2003 at 08:07:15AM -0600, ron minnich wrote:
On 18 Oct 2003, Eric W. Biederman wrote:
EPIA has problem with current CVS (resets when setting var mtrr), and it worked again when I reversed this change. According to the Intel System Programming Manual for PIII, bits 36-63 are reserved, and apparently C3 doesn't like it to be set.
Ok. Then this needs to be fixed. I am wondering how we code this cleanly.
I don't see much of an issue. The code in question sets bits that are reserved on just about any pentium-compatible CPU, and it should not. So we don't set those bits.
This code is used by K8 as well. K8 uses these bits to for memory over 64GB.
It's not wise to duplicate the whole file into cpu/k8 directory for a tiny constant difference.
-
ebiederman＠lnxi.com -
ron minnich -
SONE Takeshi