I plan to use the intel code as as guide, but not pull it in directly. We have source, we should do it right. I am going to take Aaron's suggestion and structure it as baytrail is structured.
FSP is fine for binary distros, but it's not a good fit if we have the ability to do the whole thing in source form.
ron
On Tue, Feb 25, 2014 at 5:41 AM, Stojsavljevic, Zoran < zoran.stojsavljevic@intel.com> wrote:
-----Original Message-----
From: coreboot-bounces@coreboot.org [mailto:
coreboot-bounces@coreboot.org] On Behalf Of Patrick Georgi
Sent: Tuesday, February 25, 2014 1:13 PM To: coreboot@coreboot.org Subject: Re: [coreboot] how to model the Quark architecture
One problem is that in coreboot development we care about style
(although there will be disagreement to which degree).
And not just in a formal way (which indent could solve), but I'd rather
not see things like
(BIT31 | BIT30 | BIT29 | .. all the way down to .. | BIT 1 | BIT 0) in
our tree.
While looking terribly enterprisey, it's just terrible. Intel code, at least as far as it is public and not part of the Linux
kernel, manages to collect all the horrible code standards in a single place.
I can imagine... Myself, I started looking into the some INTEL source code, and... But maybe for Quark FSP, there are only three functions which need to wrap the above mentioned Quark source code, as per general FSP spec: ROM stage - FSP calls: TempRamInitEntry(); FspInitEntry();
RAM stage - FSP calls: NotifyPhaseEntry() - twice invoked!
Maybe this can isolate (temporarily) the coding style problem, and expose just FSP I/F - APIs as they are created by FSP spec (as to support and unify access for other binary FSP blobs) for another CPUs... For the very beginning!
This what I have proposed binds to current Coreboot FSP support/framework for other INTEL CPUs (and can be easily cloned/replicated for Quark framework, for/per the current INTEL architecture)... I hope!
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