Patch set updated for coreboot: ff29084 Fixes and Sandybridge support for lapic cpu init

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/871

-gerrit

commit ff290840a59fd26c3f4da4095344e0429d402866
Author: Stefan Reinauer 
Date:   Tue Apr 3 16:17:11 2012 -0700

Fixes and Sandybridge support for lapic cpu init

- preprocessor macros should not use defined(CONFIG_*) but
      just CONFIG_*
    - skip some delays on Sandybridge systems
    - Count how long we're waiting for each AP to stop
    - Skip speedstep specific CPU entries

Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d
    Signed-off-by: Stefan Reinauer 
    Signed-off-by: Duncan Laurie 
---
 src/cpu/intel/speedstep/chip.h     |   35 +++++++++++++++++++++++++++++++++++
 src/cpu/x86/lapic/lapic_cpu_init.c |   13 ++++++++++---
 2 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/src/cpu/intel/speedstep/chip.h b/src/cpu/intel/speedstep/chip.h
new file mode 100644
index 0000000..44f336a
--- /dev/null
+++ b/src/cpu/intel/speedstep/chip.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_intel_speedstep_ops;
+
+/* Magic value used to locate this chip in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+struct cpu_intel_speedstep_config {
+	u8 pstate_coord_type;	/* Processor Coordination Type */
+
+	int c1_battery;		/* CPU C-state for ACPI C1 on Battery Power */
+	int c2_battery;		/* CPU C-state for ACPI C2 on Battery Power */
+	int c3_battery;		/* CPU C-state for ACPI C3 on Battery Power */
+
+	int c1_acpower;		/* CPU C-state for ACPI C1 on AC Power */
+	int c2_acpower;		/* CPU C-state for ACPI C2 on AC Power */
+	int c3_acpower;		/* CPU C-state for ACPI C3 on AC Power */
+};
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index ed9940c..61a0f87 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -14,6 +14,7 @@
 #include <smp/atomic.h>
 #include <smp/spinlock.h>
 #include <cpu/cpu.h>
+#include <cpu/intel/speedstep/chip.h>

#if CONFIG_SMP == 1
 /* This is a lot more paranoid now, since Linux can NOT handle
@@ -108,7 +109,7 @@ static int lapic_start_cpu(unsigned long apicid)
    	}
    	return 0;
    }
-#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
+#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX && !CONFIG_CPU_INTEL_MODEL_206AX
    mdelay(10);
 #endif

@@ -136,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid)

start_eip = get_valid_start_eip((unsigned long)_secondary_start);

-#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
+#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX
    num_starts = 2;
 #else
    num_starts = 1;
@@ -446,6 +447,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
 {
    device_t cpu;
    int old_active_count, active_count;
+	long loopcount = 0;
+
    /* Now loop until the other cpus have finished initializing */
    old_active_count = 1;
    active_count = atomic_read(&active_cpus);
@@ -456,17 +459,21 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
    	}
    	udelay(10);
    	active_count = atomic_read(&active_cpus);
+		loopcount++;
    }
    for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
    	if (cpu->path.type != DEVICE_PATH_APIC) {
    		continue;
    	}
+		if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) {
+			continue;
+		}
    	if (!cpu->initialized) {
    		printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
    			cpu->path.apic.apic_id);
    	}
    }
-	printk(BIOS_DEBUG, "All AP CPUs stopped\n");
+	printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount);
 }

#else /* CONFIG_SMP */