Patch set updated for coreboot: d9288f5 Supermicro H8QGI: Substract 1 from MMCONF range limit

[Aladyshev Konstantin]

Aladyshev Konstantin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2193

-gerrit

commit d9288f5757e3f1ab5d4b4e85ad8171502d137f87
Author: Konstantin Aladyshev 
Date:   Fri Jan 25 19:20:51 2013 +0400

Supermicro H8QGI: Substract 1 from MMCONF range limit

MMCONF space is defined by two config parameters:
    MMCONF_BASE_ADDRESS (0xF800 0000)
    MMCONF_BUS_NUMBER (64)

Coreboot allocates 1MB per bus, so MMCONF limit should be:
    0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF

Current code does not have (-1) component, this makes MMCONF limit
    equal 0xFC00 FFFF. Add (-1) to correct this issue.

No functionality change has been experienced. The five times
    slower RAM speed compared to the proprietary vendor BIOS still
    remains.

Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9
    Signed-off-by: Konstantin Aladyshev 
---
 src/mainboard/supermicro/h8qgi/agesawrapper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index 9720bed..517e136 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -147,7 +147,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
    	 * coreboot not implemente the range by range setting yet.
    	 */
    	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
-		PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus
+		PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus
    	PciData = (PciData >> 8) & 0xFFFFFF00;
    	PciData |= 0x80; //NP
    	PciData |= sblink << 4;