I am trying to implement CAR on VIA C3 / C7 cpu. After DRAM initialization, resetting the CACHE and switching the stack to DRAM, the system will hang. How can i do? Any suggestions?
VIA C3/C7 cpu 64k L1 Data Cache, 64K L1 Instruction Cache 128K L2 Cache with 32-way set associativity
Thanks
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Hi,
side note: could you try sending emails in ascii or utf8? It is hard for many on this list to read this mail otherwise..
I am trying to implement CAR on VIA C3 / C7 cpu.
good!
After DRAM initialization, resetting the CACHE and switching the stack to DRAM, the system will hang. How can i do? Any suggestions?
Is there any code we can look at? It is hard to guess the right solution without knowing how you do it.. ;-)