5 Jan
2015
5 Jan
'15
1:49 p.m.
Hello Fei,
Thanks for your answer. Indeed, the INCLUDE_ME and ME_PATH are not configured, because I do not really know what is the constitution of a "descriptor.bin" file.
May anybody have any pointer which could explain me what it is ?
Thanks in advance. Kind regards, Patrick
Le 05/01/2015 13:40, WANG FEI a écrit :
Patrick,
The below message is reading from devicetree.cb, it's not from PCI enumeration.
/- On POST 0x72 (after FSP insertion), they seem to be OK PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1/
I would suggest you hook a ITP on your Mohon Peak system and halt system before and after FSP API Init, then do a PCI scan via ITP command or script, I bet you will notice GbE devices does not exist on your system.
I remember I encountered the similar issue before, the root cause is that I did not enable the descriptor mode, as long as I enclosed a proper descriptor bin on coreboot, GbE devices can be enumerated.
Please review src\southbridge\intel\fsp_rangeley\Kconfig and make sure INCLUDE_ME and ME_PATH are configured properly.
I hope this can help you solve you the issue.
-Fei
On Mon, Jan 5, 2015 at 9:14 AM, Patrick Agrain <patrick.agrain@alcatel-lucent.com mailto:patrick.agrain@alcatel-lucent.com> wrote:
Hello all, Wish you a happy new year. Has anyone already experienced following behavior on Intel CRB Mohon Peak : - The internal GbE controllers seem not to be activated at the end of coreboot. Logs (below) shows that the ID of the controllers can not be retrieved during the PCI probe. - On POST 0x72 (after FSP insertion), they seem to be OK PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 - But after we have PCI: Static device PCI: 00:14.0 not found, disabling it. PCI: Static device PCI: 00:14.1 not found, disabling it. PCI: Static device PCI: 00:14.2 not found, disabling it. PCI: Static device PCI: 00:14.3 not found, disabling it. Note: this message is located in ./src/device/pci_device.c:pci_probe_dev() and is the result of a bad pci_read of VENDOR_ID How can this occurs ? Just for informational purpose, a tianocore version, as well as an evaluation version of an AMI BIOS for this CRB are working well. Thanks in advance for your help. Kind regards, Patrick Agrain ----------------------- Here are the relating logs from coreboot (I put almost all of them, but it is very verbose...) : coreboot-4.0-7647-gc9be93f-dirty Fri Dec 19 06:11:44 PST 2014 starting... POST: 0x41 POST: 0x42 Setting up static southbridge registers... done. Disabling Watchdog timer... done. RTC Init POST: 0x46 POST: 0x47 Starting the Intel FSP (early_init) Configure Default UPD Data PcdEnableIQAT 1 PcdEnableLan 1 PcdEnableLan 1 PcdEnableLan 1 PcdEnableLan 1 PcdEnableUsb20 1 PcdEnableSata2 1 PcdEnableSata3 1 find_current_mrc_cache_local: No valid fast boot cache found. FSP MRC cache not present. romstage_main_continue. POST: 0x48 romstage_main_continue status: 0 hob_list_ptr: 220000 FSP Status: 0x0 POST: 0x4b POST: 0x4c POST: 0x4d CBMEM: root @ 7fdff000 254 entries. POST: 0x4e POST: 0x4f Trying CBFS ramstage loader. CBFS: loading stage fallback/ramstage @ 0x100000 (258096 bytes), entry @ 0x100000 POST: 0x80 POST: 0x39 coreboot-4.0-7647-gc9be93f-dirty Fri Dec 19 06:11:44 PST 2014 booting... POST: 0x40 CBMEM: recovering 3/254 entries from root @ 7fdff000 Moving GDT to 7fdfc000...ok POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 4029 run 586 exit 0 POST: 0x71 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 587 exit 0 POST: 0x72 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: acac: enabled 0 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:17.0: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.3: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: acac: enabled 0 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:17.0: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.3: enabled 1 scan_static_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1f08] enabled Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/1f10] enabled PCI: Static device PCI: 00:02.0 not found, disabling it. Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:03.0 subordinate bus PCI Express PCI: 00:03.0 [8086/1f12] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. PCI: 00:0b.0 [8086/1f18] enabled PCI: 00:0e.0 [8086/1f14] enabled PCI: 00:0f.0 [8086/1f16] enabled PCI: 00:13.0 [8086/1f15] enabled PCI: Static device PCI: 00:14.0 not found, disabling it. PCI: Static device PCI: 00:14.1 not found, disabling it. PCI: Static device PCI: 00:14.2 not found, disabling it. PCI: Static device PCI: 00:14.3 not found, disabling it. PCI: 00:16.0 [8086/1f2c] enabled PCI: 00:17.0 [8086/0000] ops PCI: 00:17.0 [8086/1f22] enabled PCI: 00:18.0 [8086/0000] ops PCI: 00:18.0 [8086/1f32] enabled PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/1f38] enabled PCI: 00:1f.3 [8086/1f3c] bus ops PCI: 00:1f.3 [8086/1f3c] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [10de/0a65] enabled PCI: 01:00.1 [10de/0be3] enabled POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 Capability: type 0x01 @ 0x60 Capability: type 0x05 @ 0x68 Capability: type 0x10 @ 0x78 Capability: type 0x10 @ 0x40 Enabling Common Clock Configuration ASPM: Enabled L1 Capability: type 0x01 @ 0x60 Capability: type 0x05 @ 0x68 Capability: type 0x10 @ 0x78 Capability: type 0x10 @ 0x40 Enabling Common Clock Configuration ASPM: Enabled L1 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 02 POST: 0x24 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 Capability: type 0x0d @ 0xa4 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 PCI: 02:00.0 subordinate bus PCI Express PCI: 02:00.0 [10b5/8624] enabled POST: 0x25 do_pci_scan_bridge for PCI: 02:00.0 PCI: pci_scan_bus for bus 03 POST: 0x24 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 Capability: type 0x0d @ 0xa4 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 PCI: 03:04.0 subordinate bus PCI Express PCI: 03:04.0 [10b5/8624] enabled Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 Capability: type 0x0d @ 0xa4 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 PCI: 03:05.0 subordinate bus PCI Express PCI: 03:05.0 [10b5/8624] enabled Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 Capability: type 0x0d @ 0xa4 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 PCI: 03:08.0 subordinate bus PCI Express PCI: 03:08.0 [10b5/8624] enabled Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 Capability: type 0x0d @ 0xa4 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 PCI: 03:09.0 subordinate bus PCI Express PCI: 03:09.0 [10b5/8624] enabled POST: 0x25 do_pci_scan_bridge for PCI: 03:04.0 PCI: pci_scan_bus for bus 04 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=004 POST: 0x55 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 03:05.0 PCI: pci_scan_bus for bus 05 POST: 0x24 PCI: 05:00.0 [8086/1528] enabled PCI: 05:00.1 [8086/1528] enabled POST: 0x25 PCI: pci_scan_bus returning with max=005 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x11 @ 0x70 Capability: type 0x10 @ 0xa0 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 ASPM: Enabled L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x11 @ 0x70 Capability: type 0x10 @ 0xa0 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 ASPM: Enabled L1 do_pci_scan_bridge returns max 5 do_pci_scan_bridge for PCI: 03:08.0 PCI: pci_scan_bus for bus 06 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=006 POST: 0x55 do_pci_scan_bridge returns max 6 do_pci_scan_bridge for PCI: 03:09.0 PCI: pci_scan_bus for bus 07 POST: 0x24 POST: 0x25 PCI: pci_scan_bus returning with max=007 POST: 0x55 do_pci_scan_bridge returns max 7 PCI: pci_scan_bus returning with max=007 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 ASPM: Enabled None Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 ASPM: Enabled None Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 ASPM: Enabled None Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 ASPM: Enabled None do_pci_scan_bridge returns max 7 PCI: pci_scan_bus returning with max=007 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x68 Capability: type 0x10 @ 0x40 ASPM: Enabled None do_pci_scan_bridge returns max 7 scan_static_bus for PCI: 00:1f.0 scan_static_bus for PCI: 00:1f.0 done scan_static_bus for PCI: 00:1f.3 scan_static_bus for PCI: 00:1f.3 done PCI: pci_scan_bus returning with max=007 POST: 0x55 scan_static_bus for Root Device done done BS: BS_DEV_ENUMERATE times (us): entry 0 run 364879 exit 0 POST: 0x73 found VGA at PCI: 01:00.0 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 Top of Low Used DRAM (BMBOUND): 0x80000000 Top of Upper Used DRAM (BMBOUND_HI): 0x180000000 SMM memory location: 0x80000000 SMM memory size: 0x0 Subtracting 0M for SMM Available memory below 4GB: 0x7fe00000 (2046M) Available memory above 4GB: 2048M Adding PCIe config bar base=0xe0000000 size=0x10000000 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:03.0 read_resources bus 2 link: 0 PCI: 02:00.0 read_resources bus 3 link: 0 PCI: 03:04.0 read_resources bus 4 link: 0 PCI: 03:04.0 read_resources bus 4 link: 0 done PCI: 03:05.0 read_resources bus 5 link: 0 PCI: 03:05.0 read_resources bus 5 link: 0 done PCI: 03:08.0 read_resources bus 6 link: 0 PCI: 03:08.0 read_resources bus 6 link: 0 done PCI: 03:09.0 read_resources bus 7 link: 0 PCI: 03:09.0 read_resources bus 7 link: 0 done PCI: 02:00.0 read_resources bus 3 link: 0 done PCI: 00:03.0 read_resources bus 2 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: acac DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base 100000 size 7fd00000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 14 PCI: 01:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c PCI: 01:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24 PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 01:00.1 PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:02.0 PCI: 00:03.0 child on link 0 PCI: 02:00.0 PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:03.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10 PCI: 02:00.0 child on link 0 PCI: 03:04.0 PCI: 02:00.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 02:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 02:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 03:04.0 PCI: 03:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 03:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 03:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:05.0 child on link 0 PCI: 05:00.0 PCI: 03:05.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 03:05.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 03:05.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 05:00.0 PCI: 05:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 10 PCI: 05:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 05:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 PCI: 05:00.1 PCI: 05:00.1 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 10 PCI: 05:00.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 05:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 PCI: 03:08.0 PCI: 03:08.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 03:08.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 03:08.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:09.0 PCI: 03:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 03:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 03:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:04.0 PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 18 PCI: 00:0b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20 PCI: 00:0e.0 PCI: 00:0f.0 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 400 align 10 gran 10 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 PCI: 00:17.0 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:17.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24 PCI: 00:18.0 PCI: 00:18.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:18.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:18.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:18.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:18.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:18.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24 PCI: 00:1f.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffffffff flags 200 index 10 PCI: 00:1f.3 resource base efa0 size 20 align 0 gran 0 limit 0 flags f0000100 index 20 DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 01:00.0 24 * [0x0 - 0x7f] io PCI: 00:01.0 compute_resources_io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 02:00.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 03:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 03:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 03:05.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 05:00.0 18 * [0x0 - 0x1f] io PCI: 05:00.1 18 * [0x20 - 0x3f] io PCI: 03:05.0 compute_resources_io: base: 40 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 03:08.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 03:08.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 03:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 03:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 03:05.0 1c * [0x0 - 0xfff] io PCI: 02:00.0 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 02:00.0 1c * [0x0 - 0xfff] io PCI: 00:03.0 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:01.0 1c * [0x0 - 0xfff] io PCI: 00:03.0 1c * [0x1000 - 0x1fff] io PCI: 00:17.0 20 * [0x2000 - 0x201f] io PCI: 00:18.0 20 * [0x2020 - 0x203f] io PCI: 00:17.0 10 * [0x2040 - 0x2047] io PCI: 00:17.0 18 * [0x2048 - 0x204f] io PCI: 00:18.0 10 * [0x2050 - 0x2057] io PCI: 00:18.0 18 * [0x2058 - 0x205f] io PCI: 00:17.0 14 * [0x2060 - 0x2063] io PCI: 00:17.0 1c * [0x2064 - 0x2067] io PCI: 00:18.0 14 * [0x2068 - 0x206b] io PCI: 00:18.0 1c * [0x206c - 0x206f] io DOMAIN: 0000 compute_resources_io: base: 2070 size: 2070 align: 12 gran: 0 limit: ffff done DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 01:00.0 14 * [0x0 - 0xfffffff] prefmem PCI: 01:00.0 1c * [0x10000000 - 0x11ffffff] prefmem PCI: 00:01.0 compute_resources_prefmem: base: 12000000 size: 12000000 align: 28 gran: 20 limit: ffffffffffffffff done PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0xffffff] mem PCI: 01:00.0 30 * [0x1000000 - 0x107ffff] mem PCI: 01:00.1 10 * [0x1080000 - 0x1083fff] mem PCI: 00:01.0 compute_resources_mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 02:00.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 03:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 03:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 03:05.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 05:00.0 10 * [0x0 - 0x1fffff] prefmem PCI: 05:00.1 10 * [0x200000 - 0x3fffff] prefmem PCI: 05:00.0 20 * [0x400000 - 0x403fff] prefmem PCI: 05:00.1 20 * [0x404000 - 0x407fff] prefmem PCI: 03:05.0 compute_resources_prefmem: base: 408000 size: 500000 align: 21 gran: 20 limit: ffffffffffffffff done PCI: 03:08.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 03:08.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 03:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 03:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 03:05.0 24 * [0x0 - 0x4fffff] prefmem PCI: 02:00.0 compute_resources_prefmem: base: 500000 size: 500000 align: 21 gran: 20 limit: ffffffffffffffff done PCI: 02:00.0 24 * [0x0 - 0x4fffff] prefmem PCI: 00:03.0 compute_resources_prefmem: base: 500000 size: 500000 align: 21 gran: 20 limit: ffffffffffffffff done PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 03:05.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:05.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 03:08.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:08.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 03:09.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:09.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 02:00.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 02:00.0 10 * [0x0 - 0x1ffff] mem PCI: 00:03.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 24 * [0x0 - 0x11ffffff] prefmem PCI: 00:01.0 20 * [0x12000000 - 0x130fffff] mem PCI: 00:03.0 24 * [0x13200000 - 0x136fffff] prefmem PCI: 00:03.0 20 * [0x13700000 - 0x137fffff] mem PCI: 00:01.0 10 * [0x13800000 - 0x1381ffff] mem PCI: 00:03.0 10 * [0x13820000 - 0x1383ffff] mem PCI: 00:0b.0 18 * [0x13840000 - 0x1385ffff] mem PCI: 00:0b.0 20 * [0x13860000 - 0x13863fff] mem PCI: 00:17.0 24 * [0x13864000 - 0x138647ff] mem PCI: 00:18.0 24 * [0x13864800 - 0x13864fff] mem PCI: 00:13.0 10 * [0x13865000 - 0x138653ff] mem PCI: 00:16.0 10 * [0x13865400 - 0x138657ff] mem PCI: 00:1f.3 10 * [0x13865800 - 0x1386581f] mem DOMAIN: 0000 compute_resources_mem: base: 13865820 size: 13865820 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 01:00.1 constrain_resources: PCI: 00:03.0 constrain_resources: PCI: 02:00.0 constrain_resources: PCI: 03:04.0 constrain_resources: PCI: 03:05.0 constrain_resources: PCI: 05:00.0 constrain_resources: PCI: 05:00.1 constrain_resources: PCI: 03:08.0 constrain_resources: PCI: 03:09.0 constrain_resources: PCI: 00:0b.0 constrain_resources: PCI: 00:0e.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:16.0 constrain_resources: PCI: 00:17.0 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:1f.0 constrain_resources: PCI: 00:1f.3 avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ef9f avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff lim->base 7fe00000 lim->limit dfffffff Setting resources... DOMAIN: 0000 allocate_resources_io: base:1000 size:2070 align:12 gran:0 limit:ef9f Assigned: PCI: 00:01.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:03.0 1c * [0x2000 - 0x2fff] io Assigned: PCI: 00:17.0 20 * [0x3000 - 0x301f] io Assigned: PCI: 00:18.0 20 * [0x3020 - 0x303f] io Assigned: PCI: 00:17.0 10 * [0x3040 - 0x3047] io Assigned: PCI: 00:17.0 18 * [0x3048 - 0x304f] io Assigned: PCI: 00:18.0 10 * [0x3050 - 0x3057] io Assigned: PCI: 00:18.0 18 * [0x3058 - 0x305f] io Assigned: PCI: 00:17.0 14 * [0x3060 - 0x3063] io Assigned: PCI: 00:17.0 1c * [0x3064 - 0x3067] io Assigned: PCI: 00:18.0 14 * [0x3068 - 0x306b] io Assigned: PCI: 00:18.0 1c * [0x306c - 0x306f] io DOMAIN: 0000 allocate_resources_io: next_base: 3070 size: 2070 align: 12 gran: 0 done PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ef9f Assigned: PCI: 01:00.0 24 * [0x1000 - 0x107f] io PCI: 00:01.0 allocate_resources_io: next_base: 1080 size: 1000 align: 12 gran: 12 done PCI: 00:03.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ef9f Assigned: PCI: 02:00.0 1c * [0x2000 - 0x2fff] io PCI: 00:03.0 allocate_resources_io: next_base: 3000 size: 1000 align: 12 gran: 12 done PCI: 02:00.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ef9f Assigned: PCI: 03:05.0 1c * [0x2000 - 0x2fff] io PCI: 02:00.0 allocate_resources_io: next_base: 3000 size: 1000 align: 12 gran: 12 done PCI: 03:04.0 allocate_resources_io: base:ef9f size:0 align:12 gran:12 limit:ef9f PCI: 03:04.0 allocate_resources_io: next_base: ef9f size: 0 align: 12 gran: 12 done PCI: 03:05.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ef9f Assigned: PCI: 05:00.0 18 * [0x2000 - 0x201f] io Assigned: PCI: 05:00.1 18 * [0x2020 - 0x203f] io PCI: 03:05.0 allocate_resources_io: next_base: 2040 size: 1000 align: 12 gran: 12 done PCI: 03:08.0 allocate_resources_io: base:ef9f size:0 align:12 gran:12 limit:ef9f PCI: 03:08.0 allocate_resources_io: next_base: ef9f size: 0 align: 12 gran: 12 done PCI: 03:09.0 allocate_resources_io: base:ef9f size:0 align:12 gran:12 limit:ef9f PCI: 03:09.0 allocate_resources_io: next_base: ef9f size: 0 align: 12 gran: 12 done DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:13865820 align:28 gran:0 limit:dfffffff Assigned: PCI: 00:01.0 24 * [0xc0000000 - 0xd1ffffff] prefmem Assigned: PCI: 00:01.0 20 * [0xd2000000 - 0xd30fffff] mem Assigned: PCI: 00:03.0 24 * [0xd3200000 - 0xd36fffff] prefmem Assigned: PCI: 00:03.0 20 * [0xd3700000 - 0xd37fffff] mem Assigned: PCI: 00:01.0 10 * [0xd3800000 - 0xd381ffff] mem Assigned: PCI: 00:03.0 10 * [0xd3820000 - 0xd383ffff] mem Assigned: PCI: 00:0b.0 18 * [0xd3840000 - 0xd385ffff] mem Assigned: PCI: 00:0b.0 20 * [0xd3860000 - 0xd3863fff] mem Assigned: PCI: 00:17.0 24 * [0xd3864000 - 0xd38647ff] mem Assigned: PCI: 00:18.0 24 * [0xd3864800 - 0xd3864fff] mem Assigned: PCI: 00:13.0 10 * [0xd3865000 - 0xd38653ff] mem Assigned: PCI: 00:16.0 10 * [0xd3865400 - 0xd38657ff] mem Assigned: PCI: 00:1f.3 10 * [0xd3865800 - 0xd386581f] mem DOMAIN: 0000 allocate_resources_mem: next_base: d3865820 size: 13865820 align: 28 gran: 0 done PCI: 00:01.0 allocate_resources_prefmem: base:c0000000 size:12000000 align:28 gran:20 limit:dfffffff Assigned: PCI: 01:00.0 14 * [0xc0000000 - 0xcfffffff] prefmem Assigned: PCI: 01:00.0 1c * [0xd0000000 - 0xd1ffffff] prefmem PCI: 00:01.0 allocate_resources_prefmem: next_base: d2000000 size: 12000000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:d2000000 size:1100000 align:24 gran:20 limit:dfffffff Assigned: PCI: 01:00.0 10 * [0xd2000000 - 0xd2ffffff] mem Assigned: PCI: 01:00.0 30 * [0xd3000000 - 0xd307ffff] mem Assigned: PCI: 01:00.1 10 * [0xd3080000 - 0xd3083fff] mem PCI: 00:01.0 allocate_resources_mem: next_base: d3084000 size: 1100000 align: 24 gran: 20 done PCI: 00:03.0 allocate_resources_prefmem: base:d3200000 size:500000 align:21 gran:20 limit:dfffffff Assigned: PCI: 02:00.0 24 * [0xd3200000 - 0xd36fffff] prefmem PCI: 00:03.0 allocate_resources_prefmem: next_base: d3700000 size: 500000 align: 21 gran: 20 done PCI: 02:00.0 allocate_resources_prefmem: base:d3200000 size:500000 align:21 gran:20 limit:dfffffff Assigned: PCI: 03:05.0 24 * [0xd3200000 - 0xd36fffff] prefmem PCI: 02:00.0 allocate_resources_prefmem: next_base: d3700000 size: 500000 align: 21 gran: 20 done PCI: 03:04.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 03:04.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 03:05.0 allocate_resources_prefmem: base:d3200000 size:500000 align:21 gran:20 limit:dfffffff Assigned: PCI: 05:00.0 10 * [0xd3200000 - 0xd33fffff] prefmem Assigned: PCI: 05:00.1 10 * [0xd3400000 - 0xd35fffff] prefmem Assigned: PCI: 05:00.0 20 * [0xd3600000 - 0xd3603fff] prefmem Assigned: PCI: 05:00.1 20 * [0xd3604000 - 0xd3607fff] prefmem PCI: 03:05.0 allocate_resources_prefmem: next_base: d3608000 size: 500000 align: 21 gran: 20 done PCI: 03:08.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 03:08.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 03:09.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 03:09.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_mem: base:d3700000 size:100000 align:20 gran:20 limit:dfffffff Assigned: PCI: 02:00.0 10 * [0xd3700000 - 0xd371ffff] mem PCI: 00:03.0 allocate_resources_mem: next_base: d3720000 size: 100000 align: 20 gran: 20 done PCI: 02:00.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 02:00.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 03:04.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 03:04.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 03:05.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 03:05.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 03:08.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 03:08.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done PCI: 03:09.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff PCI: 03:09.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 Top of Low Used DRAM (BMBOUND): 0x80000000 Top of Upper Used DRAM (BMBOUND_HI): 0x180000000 SMM memory location: 0x80000000 SMM memory size: 0x0 Subtracting 0M for SMM Available memory below 4GB: 0x7fe00000 (2046M) Available memory above 4GB: 2048M Adding PCIe config bar base=0xe0000000 size=0x10000000 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00c0000000 - 0x00d1ffffff] size 0x12000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00d2000000 - 0x00d30fffff] size 0x01100000 gran 0x14 bus 01 mem PCI: 00:01.0 10 <- [0x00d3800000 - 0x00d381ffff] size 0x00020000 gran 0x11 mem64 PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00d2000000 - 0x00d2ffffff] size 0x01000000 gran 0x18 mem PCI: 01:00.0 14 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 01:00.0 1c <- [0x00d0000000 - 0x00d1ffffff] size 0x02000000 gran 0x19 prefmem64 PCI: 01:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io PCI: 01:00.0 30 <- [0x00d3000000 - 0x00d307ffff] size 0x00080000 gran 0x13 romem PCI: 01:00.1 10 <- [0x00d3080000 - 0x00d3083fff] size 0x00004000 gran 0x0e mem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 00:03.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 02 io PCI: 00:03.0 24 <- [0x00d3200000 - 0x00d36fffff] size 0x00500000 gran 0x14 bus 02 prefmem PCI: 00:03.0 20 <- [0x00d3700000 - 0x00d37fffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:03.0 10 <- [0x00d3820000 - 0x00d383ffff] size 0x00020000 gran 0x11 mem64 PCI: 00:03.0 assign_resources, bus 2 link: 0 PCI: 02:00.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io PCI: 02:00.0 24 <- [0x00d3200000 - 0x00d36fffff] size 0x00500000 gran 0x14 bus 03 prefmem PCI: 02:00.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 03 mem PCI: 02:00.0 10 <- [0x00d3700000 - 0x00d371ffff] size 0x00020000 gran 0x11 mem PCI: 02:00.0 assign_resources, bus 3 link: 0 PCI: 03:04.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 04 io PCI: 03:04.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 03:04.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 04 mem PCI: 03:05.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 05 io PCI: 03:05.0 24 <- [0x00d3200000 - 0x00d36fffff] size 0x00500000 gran 0x14 bus 05 prefmem PCI: 03:05.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 03:05.0 assign_resources, bus 5 link: 0 PCI: 05:00.0 10 <- [0x00d3200000 - 0x00d33fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 05:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 05:00.0 20 <- [0x00d3600000 - 0x00d3603fff] size 0x00004000 gran 0x0e prefmem64 PCI: 05:00.1 10 <- [0x00d3400000 - 0x00d35fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 05:00.1 18 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io PCI: 05:00.1 20 <- [0x00d3604000 - 0x00d3607fff] size 0x00004000 gran 0x0e prefmem64 PCI: 03:05.0 assign_resources, bus 5 link: 0 PCI: 03:08.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 06 io PCI: 03:08.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 06 prefmem PCI: 03:08.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 06 mem PCI: 03:09.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 07 io PCI: 03:09.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 07 prefmem PCI: 03:09.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 07 mem PCI: 02:00.0 assign_resources, bus 3 link: 0 PCI: 00:03.0 assign_resources, bus 2 link: 0 PCI: 00:0b.0 18 <- [0x00d3840000 - 0x00d385ffff] size 0x00020000 gran 0x11 mem64 PCI: 00:0b.0 20 <- [0x00d3860000 - 0x00d3863fff] size 0x00004000 gran 0x0e mem64 PCI: 00:13.0 10 <- [0x00d3865000 - 0x00d38653ff] size 0x00000400 gran 0x0a mem64 PCI: 00:16.0 10 <- [0x00d3865400 - 0x00d38657ff] size 0x00000400 gran 0x0a mem PCI: 00:17.0 10 <- [0x0000003040 - 0x0000003047] size 0x00000008 gran 0x03 io PCI: 00:17.0 14 <- [0x0000003060 - 0x0000003063] size 0x00000004 gran 0x02 io PCI: 00:17.0 18 <- [0x0000003048 - 0x000000304f] size 0x00000008 gran 0x03 io PCI: 00:17.0 1c <- [0x0000003064 - 0x0000003067] size 0x00000004 gran 0x02 io PCI: 00:17.0 20 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io PCI: 00:17.0 24 <- [0x00d3864000 - 0x00d38647ff] size 0x00000800 gran 0x0b mem PCI: 00:18.0 10 <- [0x0000003050 - 0x0000003057] size 0x00000008 gran 0x03 io PCI: 00:18.0 14 <- [0x0000003068 - 0x000000306b] size 0x00000004 gran 0x02 io PCI: 00:18.0 18 <- [0x0000003058 - 0x000000305f] size 0x00000008 gran 0x03 io PCI: 00:18.0 1c <- [0x000000306c - 0x000000306f] size 0x00000004 gran 0x02 io PCI: 00:18.0 20 <- [0x0000003020 - 0x000000303f] size 0x00000020 gran 0x05 io PCI: 00:18.0 24 <- [0x00d3864800 - 0x00d3864fff] size 0x00000800 gran 0x0b mem PCI: 00:1f.3 10 <- [0x00d3865800 - 0x00d386581f] size 0x00000020 gran 0x05 mem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: acac DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 2070 align 12 gran 0 limit ef9f flags 40040100 index 10000000 DOMAIN: 0000 resource base c0000000 size 13865820 align 28 gran 0 limit dfffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 DOMAIN: 0000 resource base 100000 size 7fd00000 align 0 gran 0 limit 0 flags e0004200 index 1 DOMAIN: 0000 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 3 DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 4 DOMAIN: 0000 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5 DOMAIN: 0000 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base 100000 size 7fd00000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit ef9f flags 60080102 index 1c PCI: 00:01.0 resource base c0000000 size 12000000 align 28 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:01.0 resource base d2000000 size 1100000 align 24 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:01.0 resource base d3800000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10 PCI: 01:00.0 PCI: 01:00.0 resource base d2000000 size 1000000 align 24 gran 24 limit dfffffff flags 60000200 index 10 PCI: 01:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 14 PCI: 01:00.0 resource base d0000000 size 2000000 align 25 gran 25 limit dfffffff flags 60001201 index 1c PCI: 01:00.0 resource base 1000 size 80 align 7 gran 7 limit ef9f flags 60000100 index 24 PCI: 01:00.0 resource base d3000000 size 80000 align 19 gran 19 limit dfffffff flags 60002200 index 30 PCI: 01:00.1 PCI: 01:00.1 resource base d3080000 size 4000 align 14 gran 14 limit dfffffff flags 60000200 index 10 PCI: 00:02.0 PCI: 00:03.0 child on link 0 PCI: 02:00.0 PCI: 00:03.0 resource base 2000 size 1000 align 12 gran 12 limit ef9f flags 60080102 index 1c PCI: 00:03.0 resource base d3200000 size 500000 align 21 gran 20 limit dfffffff flags 60081202 index 24 PCI: 00:03.0 resource base d3700000 size 100000 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:03.0 resource base d3820000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 10 PCI: 02:00.0 child on link 0 PCI: 03:04.0 PCI: 02:00.0 resource base 2000 size 1000 align 12 gran 12 limit ef9f flags 60080102 index 1c PCI: 02:00.0 resource base d3200000 size 500000 align 21 gran 20 limit dfffffff flags 60081202 index 24 PCI: 02:00.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 02:00.0 resource base d3700000 size 20000 align 17 gran 17 limit dfffffff flags 60000200 index 10 PCI: 03:04.0 PCI: 03:04.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c PCI: 03:04.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 03:04.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 03:05.0 child on link 0 PCI: 05:00.0 PCI: 03:05.0 resource base 2000 size 1000 align 12 gran 12 limit ef9f flags 60080102 index 1c PCI: 03:05.0 resource base d3200000 size 500000 align 21 gran 20 limit dfffffff flags 60081202 index 24 PCI: 03:05.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 05:00.0 PCI: 05:00.0 resource base d3200000 size 200000 align 21 gran 21 limit dfffffff flags 60001201 index 10 PCI: 05:00.0 resource base 2000 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18 PCI: 05:00.0 resource base d3600000 size 4000 align 14 gran 14 limit dfffffff flags 60001201 index 20 PCI: 05:00.1 PCI: 05:00.1 resource base d3400000 size 200000 align 21 gran 21 limit dfffffff flags 60001201 index 10 PCI: 05:00.1 resource base 2020 size 20 align 5 gran 5 limit ef9f flags 60000100 index 18 PCI: 05:00.1 resource base d3604000 size 4000 align 14 gran 14 limit dfffffff flags 60001201 index 20 PCI: 03:08.0 PCI: 03:08.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c PCI: 03:08.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 03:08.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 03:09.0 PCI: 03:09.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c PCI: 03:09.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24 PCI: 03:09.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20 PCI: 00:04.0 PCI: 00:0b.0 PCI: 00:0b.0 resource base d3840000 size 20000 align 17 gran 17 limit dfffffff flags 60000201 index 18 PCI: 00:0b.0 resource base d3860000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 20 PCI: 00:0e.0 PCI: 00:0f.0 PCI: 00:13.0 PCI: 00:13.0 resource base d3865000 size 400 align 10 gran 10 limit dfffffff flags 60000201 index 10 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 PCI: 00:16.0 PCI: 00:16.0 resource base d3865400 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 10 PCI: 00:17.0 PCI: 00:17.0 resource base 3040 size 8 align 3 gran 3 limit ef9f flags 60000100 index 10 PCI: 00:17.0 resource base 3060 size 4 align 2 gran 2 limit ef9f flags 60000100 index 14 PCI: 00:17.0 resource base 3048 size 8 align 3 gran 3 limit ef9f flags 60000100 index 18 PCI: 00:17.0 resource base 3064 size 4 align 2 gran 2 limit ef9f flags 60000100 index 1c PCI: 00:17.0 resource base 3000 size 20 align 5 gran 5 limit ef9f flags 60000100 index 20 PCI: 00:17.0 resource base d3864000 size 800 align 11 gran 11 limit dfffffff flags 60000200 index 24 PCI: 00:18.0 PCI: 00:18.0 resource base 3050 size 8 align 3 gran 3 limit ef9f flags 60000100 index 10 PCI: 00:18.0 resource base 3068 size 4 align 2 gran 2 limit ef9f flags 60000100 index 14 PCI: 00:18.0 resource base 3058 size 8 align 3 gran 3 limit ef9f flags 60000100 index 18 PCI: 00:18.0 resource base 306c size 4 align 2 gran 2 limit ef9f flags 60000100 index 1c PCI: 00:18.0 resource base 3020 size 20 align 5 gran 5 limit ef9f flags 60000100 index 20 PCI: 00:18.0 resource base d3864800 size 800 align 11 gran 11 limit dfffffff flags 60000200 index 24 PCI: 00:1f.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:1f.3 PCI: 00:1f.3 resource base d3865800 size 20 align 5 gran 5 limit dfffffff flags 60000200 index 10 PCI: 00:1f.3 resource base efa0 size 20 align 0 gran 0 limit 0 flags f0000100 index 20 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1749749 exit 0 POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 0000/0000 PCI: 00:00.0 cmd <- 07 PCI: 00:01.0 bridge ctrl <- 000b PCI: 00:01.0 cmd <- 07 PCI: 00:03.0 bridge ctrl <- 0003 PCI: 00:03.0 cmd <- 07 PCI: 00:0b.0 subsystem <- 0000/0000 PCI: 00:0b.0 cmd <- 102 PCI: 00:0e.0 subsystem <- 0000/0000 PCI: 00:0e.0 cmd <- 00 PCI: 00:0f.0 cmd <- 04 PCI: 00:13.0 subsystem <- 0000/0000 PCI: 00:13.0 cmd <- 106 PCI: 00:16.0 subsystem <- 0000/0000 PCI: 00:16.0 cmd <- 102 PCI: 00:17.0 subsystem <- 0000/0000 PCI: 00:17.0 cmd <- 103 PCI: 00:18.0 subsystem <- 0000/0000 PCI: 00:18.0 cmd <- 103 PCI: 00:1f.0 subsystem <- 0000/0000 PCI: 00:1f.0 cmd <- 107 PCI: 00:1f.3 subsystem <- 0000/0000 PCI: 00:1f.3 cmd <- 103 PCI: 01:00.0 cmd <- 03 PCI: 01:00.1 cmd <- 02 PCI: 02:00.0 bridge ctrl <- 0003 PCI: 02:00.0 cmd <- 07 PCI: 03:04.0 bridge ctrl <- 0003 PCI: 03:04.0 cmd <- 00 PCI: 03:05.0 bridge ctrl <- 0003 PCI: 03:05.0 cmd <- 07 PCI: 03:08.0 bridge ctrl <- 0003 PCI: 03:08.0 cmd <- 00 PCI: 03:09.0 bridge ctrl <- 0003 PCI: 03:09.0 cmd <- 00 PCI: 05:00.0 cmd <- 03 PCI: 05:00.1 cmd <- 03 done. BS: BS_DEV_ENABLE times (us): entry 0 run 54672 exit 0 POST: 0x75 Initializing devices... Root Device init Root Device init 875 usecs POST: 0x75 CPU_CLUSTER: 0 init start_eip=0x00001000, code_size=0x00000031 Initializing CPU #0 CPU: vendor Intel device 406d8 CPU: family 06, model 4d, stepping 08 POST: 0x60 Enabling cache CPU: Genuine Intel(R) CPU @ 2.40GHz. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b Disabling VMX CPU: 0 has 8 cores, 1 threads per core CPU: 0 has core 2 CPU1: stack_base 00139000, stack_end 00139ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 2. After apic_write. Initializing CPU #1 Startup point 1. Waiting for send to finish... +CPU: vendor Intel device 406d8 Sending STARTUP #2 to 2. After apic_write. CPU: family 06, model 4d, stepping 08 Startup point 1. Waiting for send to finish... +POST: 0xAfter Startup. CPU: 0 has core 4 CPU2: stack_base 00138000, stack_end 00138ff8 60Asserting INIT. Waiting for send to finish... + Enabling cache CPU: Genuine Intel(R) CPU @ 2.40GHz. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x02 done. POST: 0x9b Disabling VMX Deasserting INIT. Waiting for send to finish... +CPU #1 initialized #startup loops: 2. Sending STARTUP #1 to 4. After apic_write. Initializing CPU #2 Startup point 1. Waiting for send to finish... +CPU: vendor Intel device 406d8 Sending STARTUP #2 to 4. After apic_write. CPU: family 06, model 4d, stepping 08 Startup point 1. Waiting for send to finish... +POST: 0xAfter Startup. CPU: 0 has core 6 CPU3: stack_base 00137000, stack_end 00137ff8 60Asserting INIT. Waiting for send to finish... + Enabling cache CPU: Genuine Intel(R) CPU @ 2.40GHz. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x04 done. POST: 0x9b Disabling VMX Deasserting INIT. CPU #2 initialized Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 6. After apic_write. Initializing CPU #3 Startup point 1. Waiting for send to finish... +CPU: vendor Intel device 406d8 Sending STARTUP #2 to 6. After apic_write. CPU: family 06, model 4d, stepping 08 Startup point 1. Waiting for send to finish... +POST: 0xAfter Startup. CPU: 0 has core 8 CPU4: stack_base 00136000, stack_end 00136ff8 60Asserting INIT. Waiting for send to finish... + Enabling cache CPU: Genuine Intel(R) CPU @ 2.40GHz. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x06 done. POST: 0x9b Disabling VMX Deasserting INIT. CPU #3 initialized Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 8. After apic_write. Initializing CPU #4 Startup point 1. Waiting for send to finish... +CPU: vendor Intel device 406d8 Sending STARTUP #2 to 8. After apic_write. CPU: family 06, model 4d, stepping 08 Startup point 1. Waiting for send to finish... +POST: 0xAfter Startup. CPU: 0 has core 10 CPU5: stack_base 00135000, stack_end 00135ff8 60Asserting INIT. Waiting for send to finish... + Enabling cache CPU: Genuine Intel(R) CPU @ 2.40GHz. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x08 done. POST: 0x9b Disabling VMX Deasserting INIT. CPU #4 initialized Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 10. After apic_write. Initializing CPU #5 Startup point 1. Waiting for send to finish... +CPU: vendor Intel device 406d8 Sending STARTUP #2 to 10. After apic_write. CPU: family 06, model 4d, stepping 08 Startup point 1. Waiting for send to finish... +POST: 0xAfter Startup. CPU: 0 has core 12 CPU6: stack_base 00134000, stack_end 00134ff8 60Asserting INIT. Waiting for send to finish... + Enabling cache CPU: Genuine Intel(R) CPU @ 2.40GHz. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x0a done. POST: 0x9b Disabling VMX Deasserting INIT. CPU #5 initialized Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 12. After apic_write. Initializing CPU #6 Startup point 1. Waiting for send to finish... +CPU: vendor Intel device 406d8 Sending STARTUP #2 to 12. After apic_write. CPU: family 06, model 4d, stepping 08 Startup point 1. Waiting for send to finish... +POST: 0xAfter Startup. CPU: 0 has core 14 CPU7: stack_base 00133000, stack_end 00133ff8 60Asserting INIT. Waiting for send to finish... + Enabling cache CPU: Genuine Intel(R) CPU @ 2.40GHz. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x0c done. POST: 0x9b Disabling VMX Deasserting INIT. CPU #6 initialized Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 14. After apic_write. Initializing CPU #7 Startup point 1. Waiting for send to finish... +CPU: vendor Intel device 406d8 Sending STARTUP #2 to 14. After apic_write. CPU: family 06, model 4d, stepping 08 Startup point 1. Waiting for send to finish... +POST: 0xAfter Startup. CPU #0 initialized Waiting for 1 CPUS to stop 60 Enabling cache CPU: Genuine Intel(R) CPU @ 2.40GHz. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x0e done. POST: 0x9b Disabling VMX CPU #7 initialized All AP CPUs stopped (1151 loops) CPU1: stack: 00139000 - 0013a000, lowest used address 00139d18, stack used: 744 bytes CPU2: stack: 00138000 - 00139000, lowest used address 00138d18, stack used: 744 bytes CPU3: stack: 00137000 - 00138000, lowest used address 00137d18, stack used: 744 bytes CPU4: stack: 00136000 - 00137000, lowest used address 00136d18, stack used: 744 bytes CPU5: stack: 00135000 - 00136000, lowest used address 00135d18, stack used: 744 bytes CPU6: stack: 00134000 - 00135000, lowest used address 00134d18, stack used: 744 bytes CPU7: stack: 00133000 - 00134000, lowest used address 00133d18, stack used: 744 bytes CPU_CLUSTER: 0 init 313669 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init PCI: 00:00.0 init 924 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:0b.0 init PCI: 00:0b.0 init 923 usecs POST: 0x75 PCI: 00:0e.0 init PCI: 00:0e.0 init 923 usecs POST: 0x75 PCI: 00:0f.0 init PCI: 00:0f.0 init 923 usecs POST: 0x75 PCI: 00:13.0 init PCI: 00:13.0 init 924 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:16.0 init PCI: 00:16.0 init 923 usecs POST: 0x75 PCI: 00:17.0 init SATA: Initializing... SATA: Controller in AHCI mode. ABAR: D3864000 PCI: 00:17.0 init 4378 usecs POST: 0x75 PCI: 00:18.0 init SATA: Initializing... SATA: Controller in AHCI mode. ABAR: D3864800 PCI: 00:18.0 init 4377 usecs POST: 0x75 PCI: 00:1f.0 init soc: lpc_init Southbridge APIC ID = 2 Dumping IOAPIC registers reg 0x0000: 0x02000000 reg 0x0001: 0x00170020 reg 0x0002: 0x00170020 Start writing IRQ assignments PIRQ A B C D E F G H IRQ 10 11 10 11 14 15 14 15 PIRQ[A-H] routed to each INT_PIN[A-D] Dev INTA (IRQ) INTB (IRQ) INTC (IRQ) INTD (IRQ) 1: A (10) B (11) C (10) D (11) 2: D (11) C (10) B (11) A (10) 3: E (14) F (15) G (14) H (15) 4: H (15) G (14) F (15) E (14) 11: E (14) F (15) G (14) H (15) 14: H (15) A (10) A (10) A (10) 19: B (11) A (10) A (10) A (10) 20: C (10) D (11) E (14) F (15) 22: G (14) A (10) A (10) A (10) 23: H (15) A (10) A (10) A (10) 31: H (15) G (14) B (11) C (10) Finished writing IRQ assignments PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : A INT_LINE : 0xA (IRQ 10) PCI IRQ: Found device 0:03.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : E INT_LINE : 0xE (IRQ 14) PCI IRQ: Found device 0:0B.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : E INT_LINE : 0xE (IRQ 14) PCI IRQ: Found device 0:13.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : B INT_LINE : 0xB (IRQ 11) PCI IRQ: Found device 0:16.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : G INT_LINE : 0xE (IRQ 14) PCI IRQ: Found device 0:17.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : H INT_LINE : 0xF (IRQ 15) PCI IRQ: Found device 0:18.00 using PIN A Warning: PCI Device 24 does not have an IRQ entry, skipping it PCI IRQ: Found device 0:1F.03 using PIN B INT_PIN : 2 (PIN B) PIRQ : G INT_LINE : 0xE (IRQ 14) PCI IRQ: Found device 0:0F.00 using PIN A Warning: PCI Device 15 does not have an IRQ entry, skipping it PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:01h.00h INT_PIN : 1 (PIN A) Swizzled to : 1 (PIN A) PIRQ : A INT_LINE : 0xA (IRQ 10) PCI IRQ: Found device 1:00.01 using PIN B With INT_PIN swizzled to PIN B Attached to bridge device 0:01h.00h INT_PIN : 2 (PIN B) Swizzled to : 2 (PIN B) PIRQ : B INT_LINE : 0xB (IRQ 11) PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:03h.00h INT_PIN : 1 (PIN A) Swizzled to : 1 (PIN A) PIRQ : E INT_LINE : 0xE (IRQ 14) PCI IRQ: Found device 3:04.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 2:00h.00h With INT_PIN swizzled to PIN A Attached to bridge device 0:03h.00h INT_PIN : 1 (PIN A) Swizzled to : 1 (PIN A) PIRQ : E INT_LINE : 0xE (IRQ 14) PCI IRQ: Found device 3:05.00 using PIN A With INT_PIN swizzled to PIN B Attached to bridge device 2:00h.00h With INT_PIN swizzled to PIN B Attached to bridge device 0:03h.00h INT_PIN : 1 (PIN A) Swizzled to : 2 (PIN B) PIRQ : F INT_LINE : 0xF (IRQ 15) PCI IRQ: Found device 3:08.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 2:00h.00h With INT_PIN swizzled to PIN A Attached to bridge device 0:03h.00h INT_PIN : 1 (PIN A) Swizzled to : 1 (PIN A) PIRQ : E INT_LINE : 0xE (IRQ 14) PCI IRQ: Found device 3:09.00 using PIN A With INT_PIN swizzled to PIN B Attached to bridge device 2:00h.00h With INT_PIN swizzled to PIN B Attached to bridge device 0:03h.00h INT_PIN : 1 (PIN A) Swizzled to : 2 (PIN B) PIRQ : F INT_LINE : 0xF (IRQ 15) PCI IRQ: Found device 5:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 3:05h.00h With INT_PIN swizzled to PIN B Attached to bridge device 2:00h.00h With INT_PIN swizzled to PIN B Attached to bridge device 0:03h.00h INT_PIN : 1 (PIN A) Swizzled to : 2 (PIN B) PIRQ : F INT_LINE : 0xF (IRQ 15) PCI IRQ: Found device 5:00.01 using PIN B With INT_PIN swizzled to PIN B Attached to bridge device 3:05h.00h With INT_PIN swizzled to PIN C Attached to bridge device 2:00h.00h With INT_PIN swizzled to PIN C Attached to bridge device 0:03h.00h INT_PIN : 2 (PIN B) Swizzled to : 3 (PIN C) PIRQ : G INT_LINE : 0xE (IRQ 14) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments NMI sources disabled. Enabling BIOS updates outside of SMM... PCI: 00:1f.0 init 213502 usecs POST: 0x75 POST: 0x75 PCI: 01:00.0 init PCI: 01:00.0 init 923 usecs POST: 0x75 PCI: 01:00.1 init PCI: 01:00.1 init 924 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 05:00.0 init PCI: 05:00.0 init 923 usecs POST: 0x75 PCI: 05:00.1 init PCI: 05:00.1 init 924 usecs Devices initialized Show all devs...After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: acac: enabled 0 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 0 PCI: 00:03.0: enabled 1 PCI: 00:04.0: enabled 0 PCI: 00:0b.0: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:14.0: enabled 0 PCI: 00:14.1: enabled 0 PCI: 00:14.2: enabled 0 PCI: 00:14.3: enabled 0 PCI: 00:16.0: enabled 1 PCI: 00:17.0: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 01:00.0: enabled 1 PCI: 01:00.1: enabled 1 PCI: 02:00.0: enabled 1 PCI: 03:04.0: enabled 1 PCI: 03:05.0: enabled 1 PCI: 03:08.0: enabled 1 PCI: 03:09.0: enabled 1 PCI: 05:00.0: enabled 1 PCI: 05:00.1: enabled 1 APIC: 02: enabled 1 APIC: 04: enabled 1 APIC: 06: enabled 1 APIC: 08: enabled 1 APIC: 0a: enabled 1 APIC: 0c: enabled 1 APIC: 0e: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 639905 exit 0 POST: 0x76 Finalize devices... DOMAIN: 0000 final FspNotify(EnumInitPhaseAfterPciEnumeration) Returned from FspNotify(EnumInitPhaseAfterPciEnumeration) Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 8736 exit 0 POST: 0x77 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 586 exit 0 === FSP HOB Data Structure === FSP Hoblistptr: 0x220000 HOB 0x220000 is an EFI_HOB_TYPE_HANDOFF (type 0x1) HOB 0x220038 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x220100 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x220418 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x2204c0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x2204d8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x220528 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x220540 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x2206b8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x2206d0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x220718 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x220728 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x220738 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x220750 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x220760 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07 at location 0x0 with length 0xa0000 HOB 0x220790 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07 at location 0xa0000 with length 0x60000 HOB 0x2207c0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07 at location 0x100000 with length 0x7ff00000 HOB 0x2207f0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c03 at location 0x0 with length 0x80000000 HOB 0x220820 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x2211d0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x223450 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x200000 with length 0x20000 HOB 0x223480 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffff000 with length 0x1000 HOB 0x2234b0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7fff7000 with length 0x8000 HOB 0x2234e0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x2274f8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x229790 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7fff3000 with length 0x4000 HOB 0x2297c0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x229970 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffef000 with length 0x4000 HOB 0x2299a0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffeb000 with length 0x4000 HOB 0x2299d0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffe8000 with length 0x3000 HOB 0x229a00 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x229a18 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffe4000 with length 0x4000 HOB 0x229a48 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffe1000 with length 0x3000 HOB 0x229a78 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffdf000 with length 0x2000 HOB 0x229aa8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffdb000 with length 0x4000 HOB 0x229ad8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffd5000 with length 0x6000 HOB 0x229b08 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffd0000 with length 0x5000 HOB 0x229b38 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x229b48 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffcc000 with length 0x4000 HOB 0x229b78 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffc8000 with length 0x4000 HOB 0x229ba8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffc5000 with length 0x3000 HOB 0x229bd8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x229fe0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffb5000 with length 0x10000 HOB 0x22a010 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x22a120 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffb1000 with length 0x4000 HOB 0x22a150 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffae000 with length 0x3000 HOB 0x22a180 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7ffac000 with length 0x2000 HOB 0x22a1b0 is an EFI_HOB_TYPE_END_OF_HOB_LIST (type 0xffff) === End of FSP HOB Data Structure === Memory Configure Data Hob at 00227510 (size = 0x2298). Copy FSP MRC DATA to HOB (source addr 00227510, dest addr 7fdf9000, 8864 bytes) Fast boot data (includes align and checksum): <...> -- coreboot mailing list: coreboot@coreboot.org <mailto:coreboot@coreboot.org> http://www.coreboot.org/mailman/listinfo/coreboot
5 Jan
5 Jan
3:37 p.m.
New subject: Internal Ethernet controller on Mohon Peak CRB failed to get activated
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256
On Mon, 5 Jan 2015 13:49:05 +0100 Patrick Agrain patrick.agrain@alcatel-lucent.com wrote:
Hello Fei,
Thanks for your answer. Indeed, the INCLUDE_ME and ME_PATH are not configured, because I do not really know what is the constitution of a "descriptor.bin" file.
May anybody have any pointer which could explain me what it is ?
It's the intel management engine. It's does some power management and a lot "other" things. It's a cpu and has access to *everything* like ram, chipset, ...
http://www.coreboot.org/Intel_Management_Engine
Best, lynxis - -- Alexander Couzens
mail: lynxis@fe80.eu jabber: lynxis@jabber.ccc.de mobile: +4915123277221
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAEBCAAGBQJUqqGTAAoJEMKenaag34YEWukP/j0HO36Y9L/ruP2r1Jfk04Ti
RqBIP1tzWVcBEjTTJqF55bO5+Dz5sWsbqTxYfdfWxYE+EOHyxm/eET2vgYNsL4Se
XZUdw09RWGHP3nwvp0KpGgWDYn+mUhjr6zGnI6Bx+mhiW0k+T82c4IlSMJsLZhRD
e73Gzp5Br6Aa2VA9KY9HCvG7jS04eAOVG4ewVDfj1yR0UA6hTSfrmdiINU4R+BVc
wneKp5xcdKIoHNT2TrgTBefyibeiGzoltGR0dZ5B03VMxxvBT56dcsCQt7LlaOTm
48ZkkQl3/uPnISXkGXD5BDpwEOq730lNlF0ldmRG0KQpOdg0w9JE/9M9onuKU0tm
fmkrgNXWjVit7AFzay9pe0xAzzQaseJHjZ+PbA/HEziDEOYGpan0w4e+cZHjlOZM
ZO9b41yLAkTcYq9SPHu6EWoCExFXvvgZCd7u7UFrfeha+rdqcrIBqWw3WNTspVam
PSBxmotfSaPWQLhApj0n4vnZRR8Y7kid8AZE2wfyD8ro7paB8wLqYMZFtTrKQv85
QCbveDJbzMqa7s4sB1nSuoTWYQzoY2uNrZUoFZhKF1HU8nrTi+u8s5ZsqMgZZyEl
DhOFuaiA/mpVhlWEikv6T+6IEgEN5yND8LTck50MxvCMcDHJ4OEQM5k8WddXKVWo
McmgvLZ5qufpka30pafL
=WE05
-----END PGP SIGNATURE-----
7 Jan
7 Jan
5:21 p.m.
New subject: [SOLVED] Internal Ethernet controller on Mohon Peak CRB failed to get activated
Hello,
This issue is solved. Fei, your tip concerning the Intel Firmware Descriptor was good.
Another tip came from here: http://www.sublab.org/wiki/coreboot-x201/
I've found an Intel tool 'fict', with which I could build a valid descriptor (checked by the 'ifdtool'). Enabling the INCLUDE_ME and ME_PATH in coreboot does the rest.
Now, the Mohon Peak CRB boots with all internal GbE enabled and functionning.
Thank to all. Kind regards, Patrick Agrain
Le 05/01/2015 15:37, Alexander Couzens a écrit :
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256
On Mon, 5 Jan 2015 13:49:05 +0100 Patrick Agrain patrick.agrain@alcatel-lucent.com wrote:
Hello Fei,
Thanks for your answer. Indeed, the INCLUDE_ME and ME_PATH are not configured, because I do not really know what is the constitution of a "descriptor.bin" file.
May anybody have any pointer which could explain me what it is ?
It's the intel management engine. It's does some power management and a lot "other" things. It's a cpu and has access to *everything* like ram, chipset, ...
http://www.coreboot.org/Intel_Management_Engine
Best, lynxis
Alexander Couzens
mail: lynxis@fe80.eu jabber: lynxis@jabber.ccc.de mobile: +4915123277221 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2
iQIcBAEBCAAGBQJUqqGTAAoJEMKenaag34YEWukP/j0HO36Y9L/ruP2r1Jfk04Ti RqBIP1tzWVcBEjTTJqF55bO5+Dz5sWsbqTxYfdfWxYE+EOHyxm/eET2vgYNsL4Se XZUdw09RWGHP3nwvp0KpGgWDYn+mUhjr6zGnI6Bx+mhiW0k+T82c4IlSMJsLZhRD e73Gzp5Br6Aa2VA9KY9HCvG7jS04eAOVG4ewVDfj1yR0UA6hTSfrmdiINU4R+BVc wneKp5xcdKIoHNT2TrgTBefyibeiGzoltGR0dZ5B03VMxxvBT56dcsCQt7LlaOTm 48ZkkQl3/uPnISXkGXD5BDpwEOq730lNlF0ldmRG0KQpOdg0w9JE/9M9onuKU0tm fmkrgNXWjVit7AFzay9pe0xAzzQaseJHjZ+PbA/HEziDEOYGpan0w4e+cZHjlOZM ZO9b41yLAkTcYq9SPHu6EWoCExFXvvgZCd7u7UFrfeha+rdqcrIBqWw3WNTspVam PSBxmotfSaPWQLhApj0n4vnZRR8Y7kid8AZE2wfyD8ro7paB8wLqYMZFtTrKQv85 QCbveDJbzMqa7s4sB1nSuoTWYQzoY2uNrZUoFZhKF1HU8nrTi+u8s5ZsqMgZZyEl DhOFuaiA/mpVhlWEikv6T+6IEgEN5yND8LTck50MxvCMcDHJ4OEQM5k8WddXKVWo McmgvLZ5qufpka30pafL =WE05 -----END PGP SIGNATURE-----
8 Jan
8 Jan
10:46 a.m.
New subject: [SOLVED] Internal Ethernet controller on Mohon Peak CRB failed to get activated
Patrick,
It's great to know the issue has been solved with my suggestion.
Thanks your update.
-Fei
On Wed, Jan 7, 2015 at 4:21 PM, Patrick Agrain < patrick.agrain@alcatel-lucent.com> wrote:
Hello,
This issue is solved. Fei, your tip concerning the Intel Firmware Descriptor was good.
Another tip came from here: http://www.sublab.org/wiki/coreboot-x201/
I've found an Intel tool 'fict', with which I could build a valid descriptor (checked by the 'ifdtool'). Enabling the INCLUDE_ME and ME_PATH in coreboot does the rest.
Now, the Mohon Peak CRB boots with all internal GbE enabled and functionning.
Thank to all. Kind regards, Patrick Agrain
Le 05/01/2015 15:37, Alexander Couzens a écrit :
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256
On Mon, 5 Jan 2015 13:49:05 +0100 Patrick Agrain patrick.agrain@alcatel-lucent.com wrote:
Hello Fei,
Thanks for your answer. Indeed, the INCLUDE_ME and ME_PATH are not configured, because I do not really know what is the constitution of a "descriptor.bin" file.
May anybody have any pointer which could explain me what it is ?
It's the intel management engine. It's does some power management and a lot "other" things. It's a cpu and has access to *everything* like ram, chipset, ...
http://www.coreboot.org/Intel_Management_Engine
Best, lynxis
- -- Alexander Couzens
mail: lynxis@fe80.eu jabber: lynxis@jabber.ccc.de mobile: +4915123277221 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2
iQIcBAEBCAAGBQJUqqGTAAoJEMKenaag34YEWukP/j0HO36Y9L/ruP2r1Jfk04Ti RqBIP1tzWVcBEjTTJqF55bO5+Dz5sWsbqTxYfdfWxYE+EOHyxm/eET2vgYNsL4Se XZUdw09RWGHP3nwvp0KpGgWDYn+mUhjr6zGnI6Bx+mhiW0k+T82c4IlSMJsLZhRD e73Gzp5Br6Aa2VA9KY9HCvG7jS04eAOVG4ewVDfj1yR0UA6hTSfrmdiINU4R+BVc wneKp5xcdKIoHNT2TrgTBefyibeiGzoltGR0dZ5B03VMxxvBT56dcsCQt7LlaOTm 48ZkkQl3/uPnISXkGXD5BDpwEOq730lNlF0ldmRG0KQpOdg0w9JE/9M9onuKU0tm fmkrgNXWjVit7AFzay9pe0xAzzQaseJHjZ+PbA/HEziDEOYGpan0w4e+cZHjlOZM ZO9b41yLAkTcYq9SPHu6EWoCExFXvvgZCd7u7UFrfeha+rdqcrIBqWw3WNTspVam PSBxmotfSaPWQLhApj0n4vnZRR8Y7kid8AZE2wfyD8ro7paB8wLqYMZFtTrKQv85 QCbveDJbzMqa7s4sB1nSuoTWYQzoY2uNrZUoFZhKF1HU8nrTi+u8s5ZsqMgZZyEl DhOFuaiA/mpVhlWEikv6T+6IEgEN5yND8LTck50MxvCMcDHJ4OEQM5k8WddXKVWo McmgvLZ5qufpka30pafL =WE05 -----END PGP SIGNATURE-----
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
3607
days inactive
3610
days old
3 comments
3 participants
participants (3)
-
Alexander Couzens -
Patrick Agrain -
WANG FEI