[LinuxBIOS] addr_offset help

[Joseph Smith]

Can someone explain the significance of the  addr_offset variable in  
raminit.c on the i440bx and i82810? Also why is this set to 0x1d0 for  
the Mode register set (MRS)?

Thanks - Joe

[Corey Osgood]

Joseph Smith wrote:
> Can someone explain the significance of the  addr_offset variable in  
> raminit.c on the i440bx and i82810? Also why is this set to 0x1d0 for  
> the Mode register set (MRS)?
>
> Thanks - Joe

MRS is a setting within the ram that's set by reading from a certain
location while the northbridge is in MRS mode. It essentially tells the
ram what timings to run at. For the most part, the only values you'll
ever need for SDRAM are 0x1d0 for CL3 and 0x150 for CL2, but DDR and
DDR2 make more advanced use of MRS and E(xtended)MRS. Read the JEDEC
standard for more info.

-Corey

[Joseph Smith]

Quoting Corey Osgood :
> Joseph Smith wrote:
> > Can someone explain the significance of the  addr_offset variable in
> > raminit.c on the i440bx and i82810? Also why is this set to 0x1d0 for
> > the Mode register set (MRS)?
> >
> > Thanks - Joe
>
> MRS is a setting within the ram that's set by reading from a certain
> location while the northbridge is in MRS mode. It essentially tells the
> ram what timings to run at. For the most part, the only values you'll
> ever need for SDRAM are 0x1d0 for CL3 and 0x150 for CL2, but DDR and
> DDR2 make more advanced use of MRS and E(xtended)MRS. Read the JEDEC
> standard for more info.
>
> -Corey

Thanks Corey, that makes sense. Not sure how it tells the memory what  
timings to run at though. Does it tell the northbridge what timings to  
run at?

Thanks - Joe

[Corey Osgood]

Joseph Smith wrote:
> Quoting Corey Osgood :
> > Joseph Smith wrote:
> > > Can someone explain the significance of the  addr_offset variable in
> > > raminit.c on the i440bx and i82810? Also why is this set to 0x1d0 for
> > > the Mode register set (MRS)?
> > >
> > > Thanks - Joe
> >
> > MRS is a setting within the ram that's set by reading from a certain
> > location while the northbridge is in MRS mode. It essentially tells the
> > ram what timings to run at. For the most part, the only values you'll
> > ever need for SDRAM are 0x1d0 for CL3 and 0x150 for CL2, but DDR and
> > DDR2 make more advanced use of MRS and E(xtended)MRS. Read the JEDEC
> > standard for more info.
> >
> > -Corey
>
> Thanks Corey, that makes sense. Not sure how it tells the memory what
> timings to run at though. Does it tell the northbridge what timings to
> run at?
>
> Thanks - Joe

No. The northbridge should have the timing programmed in to some
register(s). The ram then needs to be told *the same* timings that the
northbridge is told for correct operation, otherwise you end up with
them trying to run out of sync. The memory is told what timings to run
at by putting the northbridge (which also puts the ram) into MRS mode
and reading from an offset, one of the two I've given above. The values
are derived from the bits explained here:
http://www.jedec.org/download/search/3_11_05_01R12.pdf (page 6). You can
see there that those values also correspond with sequential burst and a
burst length of 2 (which I didn't know until I looked this up!). In the
440bx and i810 ports we use CL3, so it should be safe for any memory
stick, optimizing memory timings should be one of those things to do
after everything else works, IMO.

-Corey

[Joseph Smith]

> > > MRS is a setting within the ram that's set by reading from a certain
> > > location while the northbridge is in MRS mode. It essentially tells the
> > > ram what timings to run at. For the most part, the only values you'll
> > > ever need for SDRAM are 0x1d0 for CL3 and 0x150 for CL2, but DDR and
> > > DDR2 make more advanced use of MRS and E(xtended)MRS. Read the JEDEC
> > > standard for more info.

What do you mean by this??
> And just realized something else, directly related to the email I just
> sent for Joe. Please change the MRS value from 0x1d0 to 0xad0. Heh, that
> could seriously bork things up, my bad.
>
> -Corey

What am I supposed to use for CL3?

Thanks - Joe

[Corey Osgood]

Joseph Smith wrote:
> > > > MRS is a setting within the ram that's set by reading from a certain
> > > > location while the northbridge is in MRS mode. It essentially tells
> > > > the
> > > > ram what timings to run at. For the most part, the only values you'll
> > > > ever need for SDRAM are 0x1d0 for CL3 and 0x150 for CL2, but DDR and
> > > > DDR2 make more advanced use of MRS and E(xtended)MRS. Read the JEDEC
> > > > standard for more info.
>
> What do you mean by this??

Think of it as setting a register in the ram. To have access to it, you
first have to send the northbridge the MRS command. While the
northbridge is in MRS mode is the only time you have access to that
register. Then the register is set by reading from the ram...except that
it doesn't really read. The northbridge, in MRS mode, interprets the
read as setting the value of the register. The value of the register is
the location that you tell it to read from. The northbridge takes care
of the process of setting the value, so that's all you need to do.
> > And just realized something else, directly related to the email I just
> > sent for Joe. Please change the MRS value from 0x1d0 to 0xad0. Heh, that
> > could seriously bork things up, my bad.
> >
> > -Corey
>
> What am I supposed to use for CL3?
>
> Thanks - Joe

That value (0xad0) is wrong. Anyways, the i810 datasheet says to use
Burst length 4 and interleaved burst. I'm not sure what the heck 0x1d0
is for, I thought I knew but I'm wrong. Anyways, 0x1d0 should at least
get the system running, just use it.

-Corey