[v2] r4765 - in trunk/coreboot-v2/src: mainboard/technexion mainboard/technexion/tim5690 mainboard/technexion/tim5690/acpi mainboard/technexion/tim8690 southbridge/amd/sb600
Author: myles Date: 2009-10-13 18:56:58 +0200 (Tue, 13 Oct 2009) New Revision: 4765
Added: trunk/coreboot-v2/src/mainboard/technexion/tim5690/ trunk/coreboot-v2/src/mainboard/technexion/tim5690/Config.lb trunk/coreboot-v2/src/mainboard/technexion/tim5690/Kconfig trunk/coreboot-v2/src/mainboard/technexion/tim5690/Makefile.inc trunk/coreboot-v2/src/mainboard/technexion/tim5690/Options.lb trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi/ trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi_tables.c trunk/coreboot-v2/src/mainboard/technexion/tim5690/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/technexion/tim5690/chip.h trunk/coreboot-v2/src/mainboard/technexion/tim5690/cmos.layout trunk/coreboot-v2/src/mainboard/technexion/tim5690/devicetree.cb trunk/coreboot-v2/src/mainboard/technexion/tim5690/fadt.c trunk/coreboot-v2/src/mainboard/technexion/tim5690/get_bus_conf.c trunk/coreboot-v2/src/mainboard/technexion/tim5690/irq_tables.c trunk/coreboot-v2/src/mainboard/technexion/tim5690/mainboard.c trunk/coreboot-v2/src/mainboard/technexion/tim5690/mptable.c trunk/coreboot-v2/src/mainboard/technexion/tim5690/resourcemap.c Modified: trunk/coreboot-v2/src/mainboard/technexion/Kconfig trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi/dsdt.asl trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi/usb.asl trunk/coreboot-v2/src/mainboard/technexion/tim8690/mainboard.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c Log: This patch support for the Technexion Tim-5690 mainboard. It's an embedded AMD RS690/SB600 mainboard.
http://www.technexion.com/index.php/tim-5690
Myles added Kconfig support.
Signed-off-by: Libra Li libra.li@technexion.com Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/coreboot-v2/src/mainboard/technexion/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/Kconfig 2009-10-13 16:47:57 UTC (rev 4764) +++ trunk/coreboot-v2/src/mainboard/technexion/Kconfig 2009-10-13 16:56:58 UTC (rev 4765) @@ -3,6 +3,7 @@ depends on VENDOR_TECHNEXION
source "src/mainboard/technexion/tim8690/Kconfig" +source "src/mainboard/technexion/tim5690/Kconfig"
endchoice
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/Config.lb (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/Config.lb 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,271 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +## +## + +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 +include /config/nofailovercalculation.lb + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +#dir /drivers/si/3114 + +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE + object get_bus_conf.o + object irq_tables.o +end + +if CONFIG_HAVE_ACPI_TABLES + object acpi_tables.o + object fadt.o + makerule dsdt.c + depends "$(CONFIG_MAINBOARD)/acpi/*.asl" + action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" + action "mv dsdt.hex dsdt.c" + end + object ./dsdt.o +end + +#object reset.o + + if CONFIG_USE_INIT + + makerule ./cache_as_ram_auto.o + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" + end + + else + + makerule ./cache_as_ram_auto.inc + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end + + end + +## +## Build our 16 bit and 32 bit coreboot entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end + +## +## Build our reset vector (This is where coreboot is entered) +## +if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + + ## + ## Setup Cache-As-Ram + ## + mainboardinit cpu/amd/car/cache_as_ram.inc + +### +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if CONFIG_USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## + if CONFIG_USE_INIT + initobject cache_as_ram_auto.o + else + mainboardinit ./cache_as_ram_auto.inc + end + +## +## Include the secondary Configuration files +## +config chip.h + +#The variables belong to mainboard are defined here. + +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff80000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_S1G1 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + chip drivers/pci/onboard + device pci 5.0 on end # Internal Graphics 0x791F + register "rom_address" = "0xfff80000" #512KB + #register "rom_address" = "0xfff00000" #1024KB + #register "rom_address" = "0xffe00000" #2048KB + #register "rom_address" = "0xffc00000" #4096KB + end + end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "vga_rom_address" = "0xfff80000" + #register "vga_rom_address" = "0xfff00000" + #register "vga_rom_address" = "0xffe00000" + #register "vga_rom_address" = "0xffc00000" + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "1" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "0" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 + end #pci_domain +end #northbridge/amd/amdk8/root_complex +
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/Config.lb ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/Kconfig (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/Kconfig) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/Kconfig 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,105 @@ +config BOARD_TECHNEXION_TIM5690 + bool "Tim5690" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_S1G1 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_RS690 + select SOUTHBRIDGE_AMD_SB600 + select SUPERIO_ITE_IT8712F + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select MEM_TRAIN_SEQ + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default technexion/tim5690 + depends on BOARD_TECHNEXION_TIM5690 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_TECHNEXION_TIM5690 + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_TECHNEXION_TIM5690 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_TECHNEXION_TIM5690 + +config APIC_ID_OFFSET + hex + default 0x8 + depends on BOARD_TECHNEXION_TIM5690 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TECHNEXION_TIM5690 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TECHNEXION_TIM5690 + +config MAINBOARD_PART_NUMBER + string + default "tim5690" + depends on BOARD_TECHNEXION_TIM5690 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TECHNEXION_TIM5690 + +config MAX_CPUS + int + default 2 + depends on BOARD_TECHNEXION_TIM5690 + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_TECHNEXION_TIM5690 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TECHNEXION_TIM5690 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TECHNEXION_TIM5690 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x6 + depends on BOARD_TECHNEXION_TIM5690 + +config HT_CHAIN_UNITID_BASE + hex + default 0xa + depends on BOARD_TECHNEXION_TIM5690 + +config USE_INIT + bool + default n + depends on BOARD_TECHNEXION_TIM5690 + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_TECHNEXION_TIM5690
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/Kconfig ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/Makefile.inc (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/Makefile.inc) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/Makefile.inc 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl + iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl + mv $(obj)/dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/.rodata/.rom.data/g' -pi $@ + perl -e 's/.text/.section .rom.text/g' -pi $@ + +endif +
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/Makefile.inc ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/Options.lb (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/Options.lb 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,301 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +## +## + +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses CONFIG_FALLBACK_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses COREBOOT_EXTRA_VERSION +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_HAVE_INIT_TIMER +uses CONFIG_GDB_STUB +uses CONFIG_GDB_STUB +uses CONFIG_CROSS_COMPILE +uses CC +uses HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_INIT + +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_USE_PRINTK_IN_CAR + +uses CONFIG_VIDEO_MB +uses CONFIG_GFXUMA +uses CONFIG_HAVE_MAINBOARD_RESOURCES +uses CONFIG_VGA_ROM_RUN + +### +### Build options +### + +## +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +## +default CONFIG_ROM_SIZE=524288 + +## +## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE + +## +## Build code for the fallback boot +## +default CONFIG_HAVE_FALLBACK_BOOT=1 + +## +## Build code to reset the motherboard from coreboot +## +default CONFIG_HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default CONFIG_HAVE_MP_TABLE=1 + +## ACPI tables will be included +default CONFIG_HAVE_ACPI_TABLES=1 + +## +## Build code to export a CMOS option table +## +default CONFIG_HAVE_OPTION_TABLE=0 + +## +## Move the default coreboot cmos range off of AMD RTC registers +## +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=2 + +default CONFIG_MAX_PHYSICAL_CPUS=1 +default CONFIG_LOGICAL_CPUS=1 + +#1G memory hole +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 + +# BTDC: Only one HT device on Herring. +#HT Unit ID offset +#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_UNITID_BASE=0x0 + + +#real SB Unit ID +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 + +#make the SB HT chain on bus 0 +default CONFIG_SB_HT_CHAIN_ON_BUS0=1 + +## +## enable CACHE_AS_RAM specifics +## +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc8000 +default CONFIG_DCACHE_RAM_SIZE=0x8000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_INIT=0 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default CONFIG_MAINBOARD_PART_NUMBER="tim5690" +default CONFIG_MAINBOARD_VENDOR="technexion" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 + + +### +### coreboot layout values +### + +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default CONFIG_STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default CONFIG_HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 + +## +## coreboot C code runs at this location in RAM +## +default CONFIG_RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_PAYLOAD = 1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + + +default CONFIG_USE_PRINTK_IN_CAR=1 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 + +# Select the serial console base port +default CONFIG_TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default CONFIG_TTYS0_LCS=0x3 + +## +### Select the coreboot loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## CONFIG_DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +default CONFIG_VIDEO_MB=1 +default CONFIG_GFXUMA=1 +default CONFIG_HAVE_MAINBOARD_RESOURCES=1 + +### End Options.lb +end
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/Options.lb ___________________________________________________________________ Added: svn:mergeinfo +
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi ___________________________________________________________________ Added: svn:mergeinfo +
Modified: trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi/dsdt.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/dsdt.asl 2009-10-12 18:43:26 UTC (rev 4761) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi/dsdt.asl 2009-10-13 16:56:58 UTC (rev 4765) @@ -23,7 +23,7 @@ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ "TECHNEXION", /* OEMID */ - "TIM-8690", /* TABLE ID */ + "TIM-5690", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -934,10 +934,10 @@ */
/* General event 3 */ - Method(_L03) { - /* DBGO("\_GPE\_L00\n") */ - Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } + //Method(_L03) { + // /* DBGO("\_GPE\_L00\n") */ + // Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + //}
/* General event 4 */ /* Method(_L04) { @@ -1610,7 +1610,7 @@ Device(PWRB) { /* Start Power button device */ Name(_HID, EISAID("PNP0C0C")) Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + //Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ Name(_STA, 0x0B) /* sata is invisible */ } } /* End _SB scope */
Modified: trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi/usb.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi/usb.asl 2009-10-12 18:43:26 UTC (rev 4761) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi/usb.asl 2009-10-13 16:56:58 UTC (rev 4765) @@ -97,17 +97,18 @@ }
/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, _SB.PT5D) - } - } - } -} +/* If (LLessEqual(UOM5,9)) { +* Scope (_GPE) { +* Method (_L1A) { +* UCOC() +* if (LEqual(GPB5,PLC5)) { +* Not(PLC5,PLC5) +* Store(PLC5, _SB.PT5D) +* } +* } +* } +* } +*/
/* USB Port 6 overcurrent uses Gpm 6 */ If (LLessEqual(UOM6,9)) {
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi_tables.c (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi_tables.c) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi_tables.c 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,291 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdk8_sysconf.h> +#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include <arch/cpu.h> +#include <cpu/amd/model_fxx_powernow.h> + +extern u16 pm_base; + +#define DUMP_ACPI_TABLES 0 + +/* +* Assume the max pstate number is 8 +* 0x21(33 bytes) is one package length of _PSS package +*/ + +#define Maxpstate 8 +#define Defpkglength 0x21 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk_debug("\n%08x:", i); + } + printk_debug(" %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern u8 AmlCode[]; + +#if CONFIG_ACPI_SSDTX_NUM >= 1 +extern u8 AmlCode_ssdt2[]; +extern u8 AmlCode_ssdt3[]; +extern u8 AmlCode_ssdt4[]; +extern u8 AmlCode_ssdt5[]; +#endif + +#define IO_APIC_ADDR 0xfec00000UL + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB600 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} + +extern void get_bus_conf(void); + +void update_ssdtx(void *ssdtx, int i) +{ + uint8_t *PCI; + uint8_t *HCIN; + uint8_t *UID; + + PCI = ssdtx + 0x32; + HCIN = ssdtx + 0x39; + UID = ssdtx + 0x40; + + if (i < 7) { + *PCI = (uint8_t) ('4' + i - 1); + } else { + *PCI = (uint8_t) ('A' + i - 1 - 6); + } + *HCIN = (uint8_t) i; + *UID = (uint8_t) (i + 3); + + /* FIXME: need to update the GSI id in the ssdtx too */ + +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16byte */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + /* If we want to use HPET Timers Linux wants an MADT */ + printk_debug("ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + printk_debug("ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + +#if 0 + /* SRAT */ + printk_debug("ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + printk_debug("ACPI: * SLIT\n"); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); +#endif + + /* SSDT */ + printk_debug("ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + +#if CONFIG_ACPI_SSDTX_NUM >= 1 + + /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ + + for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ + if ((sysconf.pci1234[i] & 1) != 1) + continue; + uint8_t c; + if (i < 7) { + c = (uint8_t) ('4' + i - 1); + } else { + c = (uint8_t) ('A' + i - 1 - 6); + } + printk_debug("ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ + current = (current + 0x07) & -0x08; + ssdtx = (acpi_header_t *) current; + switch (sysconf.hcid[i]) { + case 1: /* 8132 */ + p = AmlCode_ssdt2; + break; + case 2: /* 8151 */ + p = AmlCode_ssdt3; + break; + case 3: /* 8131 */ + p = AmlCode_ssdt4; + break; + default: + /* HTX no io apic */ + p = AmlCode_ssdt5; + break; + } + current += ((acpi_header_t *) p)->length; + memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *) p)->length); + update_ssdtx((void *)ssdtx, i); + ssdtx->checksum = 0; + ssdtx->checksum = + acpi_checksum((u8 *)ssdtx, ssdtx->length); + acpi_add_table(rsdp, ssdtx); + } +#endif + + /* FACS */ + printk_debug("ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk_debug("ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy((void *)dsdt, (void *)AmlCode, + ((acpi_header_t *) AmlCode)->length); + current += dsdt->length; + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); + /* FADT */ + printk_debug("ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + +#if DUMP_ACPI_TABLES == 1 + printk_debug("rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk_debug("rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk_debug("madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk_debug("srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk_debug("slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk_debug("ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk_debug("fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk_info("ACPI: done.\n"); + return current; +}
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/acpi_tables.c ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/cache_as_ram_auto.c (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/cache_as_ram_auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __ROMCC__ + +#define RAMINIT_SYSINFO 1 +#define K8_SET_FIDVID 1 +#define QRANK_DIMM_SUPPORT 1 +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif + +#define RC0 (6<<8) +#define RC1 (7<<8) + +#define DIMM0 0x50 +#define DIMM1 0x51 + +#define ICS951462_ADDRESS 0x69 +#define SMBUS_HUB 0x71 + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" + +#define post_code(x) outb(x, 0x80) + +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/ite/it8712f/it8712f_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#include "southbridge/amd/rs690/rs690_early_setup.c" +#include "southbridge/amd/sb600/sb600_early_setup.c" + +/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +/* called in raminit_f.c */ +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +/*called in raminit_f.c */ +static inline int spd_read_byte(u32 device, u32 address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/raminit_f.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "lib/generic_sdram.c" +#include "resourcemap.c" + +#include "cpu/amd/dualcore/dualcore.c" + +#include "cpu/amd/car/copy_and_run.c" +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + +#include "cpu/amd/model_fxx/fidvid.c" + +#if CONFIG_USE_FALLBACK_IMAGE == 1 + +#include "northbridge/amd/amdk8/early_ht.c" + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + /* Is this a cpu only reset? Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal()) { /* RTC already inited */ + goto normal_image; + } else { + goto fallback_image; + } + } + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } else { + goto fallback_image; + } +normal_image: + post_code(0x23); + __asm__ volatile ("jmp __normal_image": /* outputs */ + :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); + +fallback_image: + post_code(0x25); +} +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + +#if CONFIG_USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); +} + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; + int needs_reset = 0; + u32 bsp_apicid = 0; + msr_t msr; + struct cpuid_result cpuid1; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } + + enable_rs690_dev8(); + sb600_lpc_init(); + + /* it8712f_enable_serial does not use its 1st parameter. */ + it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + it8712f_kill_watchdog(); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + printk_debug("bsp_apicid=0x%x\n", bsp_apicid); + + setup_tim5690_resource_map(); + + setup_coherent_ht_domain(); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched */ + wait_all_core0_started(); + start_other_cores(); +#endif + wait_all_aps_started(bsp_apicid); + + ht_setup_chains_x(sysinfo); + + /* run _early_setup before soft-reset. */ + rs690_early_setup(); + sb600_early_setup(); + + /* Check to see if processor is capable of changing FIDVID */ + /* otherwise it will throw a GP# when reading FIDVID_STATUS */ + cpuid1 = cpuid(0x80000007); + if( (cpuid1.edx & 0x6) == 0x6 ) { + + /* Read FIDVID_STATUS */ + msr=rdmsr(0xc0010042); + printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + + /* show final fid and vid */ + msr=rdmsr(0xc0010042); + printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + } else { + printk_debug("Changing FIDVID not supported\n"); + } + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); + printk_debug("needs_reset=0x%x\n", needs_reset); + + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now; */ + printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n", + sysinfo->nodes, sysinfo->ctrl, spd_addr); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + + rs690_before_pci_init(); + sb600_before_pci_init(); + + post_cache_as_ram(); +}
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/cache_as_ram_auto.c ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/chip.h (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/chip.h) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/chip.h 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config +{ + u32 uma_size; /* How many UMA should be used in memory for TOP. */ +}; +
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/chip.h ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/cmos.layout (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/cmos.layout) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/cmos.layout (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/cmos.layout 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,119 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +## +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + +
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/cmos.layout ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/devicetree.cb (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/devicetree.cb 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,134 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff80000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_S1G1 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + chip drivers/pci/onboard + device pci 5.0 on end # Internal Graphics 0x791F + register "rom_address" = "0xfff80000" #512KB + #register "rom_address" = "0xfff00000" #1024KB + #register "rom_address" = "0xffe00000" #2048KB + #register "rom_address" = "0xffc00000" #4096KB + end + end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "vga_rom_address" = "0xfff80000" + #register "vga_rom_address" = "0xfff00000" + #register "vga_rom_address" = "0xffe00000" + #register "vga_rom_address" = "0xffc00000" + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "1" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "0" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 + end #pci_domain +end #northbridge/amd/amdk8/root_complex +
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/devicetree.cb ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/fadt.c (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/fadt.c) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/fadt.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/fadt.c 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <device/device.h> +#include <../southbridge/amd/sb600/sb600.h> + +/*extern*/ u16 pm_base = 0x800; +/* pm_base should be set in sb acpi */ +/* pm_base should be got from bar2 of rs690. Here I compact ACPI + * registers into 32 bytes limit. + * */ + +#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */ +#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */ + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + pm_base &= 0xFFFF; + printk_debug("pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF); + pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8); + pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF); + pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8); + pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF); + pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8); + pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); + pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); + + /* CpuControl is in _PR.CPU0, 6 bytes */ + pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); + pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); + + pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */ + pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */ + + pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); + pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); + + pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + * the contents of the PM registers at + * index 20-2B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); +}
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/fadt.c ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/get_bus_conf.c (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/get_bus_conf.c) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/get_bus_conf.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/get_bus_conf.c 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/dualcore.h> +#endif + +#include <cpu/amd/amdk8_sysconf.h> + +/* Global variables for MB layouts and these will be shared by irqtable mptable +* and acpi_tables busnum is default. +*/ +u8 bus_isa; +u8 bus_rs690[8]; +u8 bus_sb600[2]; +u32 apicid_sb600; + +/* +* Here you only need to set value in pci1234 for HT-IO that could be installed or not +* You may need to preset pci1234 for HTIO board, +* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +*/ +u32 pci1234x[] = { + 0x0000ff0, +}; + +/* +* HT Chain device num, actually it is unit id base of every ht device in chain, +* assume every chain only have 4 ht device at most +*/ +u32 hcdnx[] = { + 0x20202020, +}; + +u32 bus_type[256]; + +u32 sbdn_rs690; +u32 sbdn_sb600; + +extern void get_sblk_pci1234(void); + +static u32 get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + u32 apicid_base; + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + get_bus_conf_done = 1; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); + sbdn_rs690 = sysconf.sbdn; + sbdn_sb600 = 0; + + for (i = 0; i < 2; i++) { + bus_sb600[i] = 0; + } + for (i = 0; i < 8; i++) { + bus_rs690[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb600[0] = bus_rs690[0]; + + bus_type[bus_rs690[0]] = 1; + + /* sb600 */ + dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4)); + if (dev) { + bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb600[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + /* rs690 */ + for (i = 1; i < 8; i++) { + dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0)); + if (dev) { + bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_rs690[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_rs690[i]] = 1; /* PCI bus. */ + } + } + } + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(1); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + apicid_sb600 = apicid_base + 0; +}
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/get_bus_conf.c ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/irq_tables.c (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/irq_tables.c) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/irq_tables.c 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +#include <cpu/amd/amdk8_sysconf.h> + +extern void get_bus_conf(void); + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_rs690[8]; +extern u8 bus_sb600[2]; +extern unsigned long sbdn_sb600; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk_info("Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb600[0]; + pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk_info("write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +}
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/irq_tables.c ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/mainboard.c (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/mainboard.c) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/mainboard.c 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,216 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <../southbridge/amd/sb600/sb600.h> +#include "chip.h" + +#define ADT7461_ADDRESS 0x4C +#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define SMBUS_IO_BASE 0x1000 + +extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, + u8 val); +extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, + uint64_t start, uint64_t size); +#define ADT7461_read_byte(address) \ + do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) +#define ARA_read_byte(address) \ + do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) +#define ADT7461_write_byte(address, val) \ + do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) + +uint64_t uma_memory_base, uma_memory_size; + + + +/*************************************************** +* This board, the TIM-5690 has two Marvel 88e5056 PCI-E +* 10/100/1000 chips on board. +* Both of their pin PERSTn pins are connected to GPIO 5 of the +* SB600 southbridge. +****************************************************/ +static void enable_onboard_nic() +{ + + u8 byte; + device_t sm_dev; + + printk_info("enable_onboard_nic.\n"); + + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + + byte = pci_read_config8(sm_dev, 0x9a); + byte |= ( 1 << 7); + pci_write_config8(sm_dev, 0x9a, byte); + + byte=pm_ioread(0x59); + byte &= ~( 1<< 5); + pm_iowrite(0x59,byte); + + byte = pci_read_config8(sm_dev, 0xA8); + + byte |= (1 << 1); //set bit 1 to high + pci_write_config8(sm_dev, 0xA8, byte); +} + +/* set thermal config + */ +static void set_thermal_config() +{ + u8 byte; + u16 word; + device_t sm_dev; + + /* set ADT 7461 */ + ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ + ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ + ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ + ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ + + ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ + ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ + + byte = ADT7461_read_byte(0x02); /* read status register to clear it */ + ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ + printk_info("Init adt7461 end , status 0x02 %02x\n", byte); + + /* sb600 settings for thermal config */ + /* set SB600 GPIO 64 to GPIO with pull-up */ + byte = pm2_ioread(0x42); + byte &= 0x3f; + pm2_iowrite(0x42, byte); + + /* set GPIO 64 to input */ + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + word = pci_read_config16(sm_dev, 0x56); + word |= 1 << 7; + pci_write_config16(sm_dev, 0x56, word); + + /* set GPIO 64 internal pull-up */ + byte = pm2_ioread(0xf0); + byte &= 0xee; + pm2_iowrite(0xf0, byte); + + /* set Talert to be active low */ + byte = pm_ioread(0x67); + byte &= ~(1 << 5); + pm_iowrite(0x67, byte); + + /* set Talert to generate ACPI event */ + byte = pm_ioread(0x3c); + byte &= 0xf3; + pm_iowrite(0x3c, byte); + + /* THERMTRIP pin */ + /* byte = pm_ioread(0x68); + * byte |= 1 << 3; + * pm_iowrite(0x68, byte); + * + * byte = pm_ioread(0x55); + * byte |= 1 << 0; + * pm_iowrite(0x55, byte); + * + * byte = pm_ioread(0x67); + * byte &= ~( 1 << 6); + * pm_iowrite(0x67, byte); + */ +} + +/************************************************* +* enable the dedicated function in tim5690 board. +* This function called early than rs690_enable. +*************************************************/ +void tim5690_enable(device_t dev) +{ + struct mainboard_config *mainboard = + (struct mainboard_config *)dev->chip_info; + + printk_info("Mainboard tim5690 Enable. dev=0x%p\n", dev); + +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + switch (msr.lo) { + case 0x10000000: /* 256M system memory */ + uma_memory_size = 0x2000000; /* 32M recommended UMA */ + break; + + case 0x18000000: /* 384M system memory */ + uma_memory_size = 0x4000000; /* 64M recommended UMA */ + break; + + case 0x20000000: /* 512M system memory */ + uma_memory_size = 0x4000000; /* 64M recommended UMA */ + break; + + default: /* 1GB and above system memory */ + uma_memory_size = 0x8000000; /* 128M recommended UMA */ + break; + } + + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 0x8000000; /* 128M recommended UMA */ + uma_memory_base = 0x38000000; /* 1GB system memory supposed */ +#endif + + enable_onboard_nic(); + set_thermal_config(); +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, + uma_memory_base, uma_memory_size); +#endif +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("TechNexion TIM-5690 Mainboard") + .enable_dev = tim5690_enable, +};
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/mainboard.c ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/mptable.c (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/mptable.c) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/mptable.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/mptable.c 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,212 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> + +#include <cpu/amd/amdk8_sysconf.h> + +extern u8 bus_isa; +extern u8 bus_rs690[8]; +extern u8 bus_sb600[2]; + +extern u32 apicid_sb600; + +extern u32 bus_type[256]; +extern u32 sbdn_rs690; +extern u32 sbdn_sb600; + +extern void get_bus_conf(void); + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "ATI "; + static const char productid[12] = "TIM5690 "; + struct mp_config_table *mc; + int j; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + + /* Bus: Bus ID Type */ + /* define bus and isa numbers */ + for (j = 0; j < bus_isa; j++) { + smp_write_bus(mc, j, (char *)"PCI "); + } + smp_write_bus(mc, bus_isa, (char *)"ISA "); + + /* I/O APICs: APIC ID Version State Address */ + { + device_t dev; + u32 dword; + u8 byte; + + dev = + dev_find_slot(bus_sb600[0], + PCI_DEVFN(sbdn_sb600 + 0x14, 0)); + if (dev) { + dword = pci_read_config32(dev, 0x74) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sb600, 0x11, dword); + + /* Initialize interrupt mapping */ + /* aza */ + byte = pci_read_config8(dev, 0x63); + byte &= 0xf8; + byte |= 0; /* 0: INTA, ...., 7: INTH */ + pci_write_config8(dev, 0x63, byte); + + /* SATA */ + dword = pci_read_config32(dev, 0xac); + dword &= ~(7 << 26); + dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ + /* dword |= 1<<22; PIC and APIC co exists */ + pci_write_config32(dev, 0xac, dword); + + /* + * 00:12.0: PROG SATA : INT F + * 00:13.0: INTA USB_0 + * 00:13.1: INTB USB_1 + * 00:13.2: INTC USB_2 + * 00:13.3: INTD USB_3 + * 00:13.4: INTC USB_4 + * 00:13.5: INTD USB2 + * 00:14.1: INTA IDE + * 00:14.2: Prog HDA : INT E + * 00:14.5: INTB ACI + * 00:14.6: INTB MCI + */ + } + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb600, 0x0); + + /* ISA ints are edge-triggered, and usually originate from the ISA bus, + * or its remainings. + */ +#define ISA_INT(intr, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sb600, (pin)) + + ISA_INT(0x1, 0x1); + ISA_INT(0x0, 0x2); + ISA_INT(0x3, 0x3); + ISA_INT(0x4, 0x4); + ISA_INT(0x6, 0x6); + ISA_INT(0x7, 0x7); + ISA_INT(0xc, 0xc); + ISA_INT(0xd, 0xd); + ISA_INT(0xe, 0xe); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#if CONFIG_HAVE_ACPI_TABLES == 0 +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) +#else +#define PCI_INT(bus, dev, fn, pin) +#endif + + /* usb */ + PCI_INT(0x0, 0x13, 0x0, 0x10); + PCI_INT(0x0, 0x13, 0x1, 0x11); + PCI_INT(0x0, 0x13, 0x2, 0x12); + PCI_INT(0x0, 0x13, 0x3, 0x13); + + /* sata */ + PCI_INT(0x0, 0x12, 0x0, 0x16); + + /* HD Audio: b0:d20:f1:reg63 should be 0. */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* on board NIC & Slot PCIE. */ + PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12); + PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13); + PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12); + PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13); + PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10); + PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11); + PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12); + PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13); + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = + smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +}
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/mptable.c ___________________________________________________________________ Added: svn:mergeinfo +
Copied: trunk/coreboot-v2/src/mainboard/technexion/tim5690/resourcemap.c (from rev 4761, trunk/coreboot-v2/src/mainboard/technexion/tim8690/resourcemap.c) =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim5690/resourcemap.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/technexion/tim5690/resourcemap.c 2009-10-13 16:56:58 UTC (rev 4765) @@ -0,0 +1,278 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void setup_tim5690_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +}
Property changes on: trunk/coreboot-v2/src/mainboard/technexion/tim5690/resourcemap.c ___________________________________________________________________ Added: svn:mergeinfo +
Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/mainboard.c 2009-10-13 16:47:57 UTC (rev 4764) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/mainboard.c 2009-10-13 16:56:58 UTC (rev 4765) @@ -49,7 +49,7 @@
/*************************************************** -* This board, the TIM-8690 has two Marvel 88e5056 PCI-E +* This board, the TIM-8690 has two Marvel 88e5056 PCI-E * 10/100/1000 chips on board. * Both of their pin PERSTn pins are connected to GPIO 5 of the * SB600 southbridge. @@ -57,28 +57,25 @@ static void enable_onboard_nic() {
- u8 byte; - device_t sm_dev; + u8 byte; + device_t sm_dev;
+ printk_info("enable_onboard_nic.\n");
- printk_info("enable_onboard_nic.\n"); + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + byte = pci_read_config8(sm_dev, 0x9a); + byte |= ( 1 << 7); + pci_write_config8(sm_dev, 0x9a, byte);
- byte = pci_read_config8(sm_dev, 0x9a); - byte |= ( 1 << 7); - pci_write_config8(sm_dev, 0x9a, byte); + byte=pm_ioread(0x59); + byte &= ~( 1<< 5); + pm_iowrite(0x59,byte);
+ byte = pci_read_config8(sm_dev, 0xA8);
- byte=pm_ioread(0x59); - byte &= ~( 1<< 5); - pm_iowrite(0x59,byte); - - - byte = pci_read_config8(sm_dev, 0xA8); - - byte |= (1 << 1); //set bit 1 to high - pci_write_config8(sm_dev, 0xA8, byte); + byte |= (1 << 1); //set bit 1 to high + pci_write_config8(sm_dev, 0xA8, byte); }
/* set thermal config
Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c 2009-10-13 16:47:57 UTC (rev 4764) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c 2009-10-13 16:56:58 UTC (rev 4765) @@ -106,8 +106,8 @@ pci_write_config16(dev, 0x68, 0x000e); /* enable LPC ROM range mirroring end 0x000f(ffff) */ pci_write_config16(dev, 0x6a, 0x000f); - /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB */ - pci_write_config16(dev, 0x6c, 0xfff0); + /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB, 0xffe0(0000): 2MB, 0xffc0(0000): 4MB */ + pci_write_config16(dev, 0x6c, 0xffc0); /* enable LPC ROM range end at 0xffff(ffff) */ pci_write_config16(dev, 0x6e, 0xffff); }
-
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