HELP: Porting i830 RAM init to 440BX, now it won't compile

[Keith Hui]

Hi, I need help getting this "patch" to compile.

This is my attempt at porting Joseph Smith's i830 RAM init code to 440BX.
Apply this patch and you have my 440BX part of the code. Which is where all
the trouble is. I changed motherboard target to P2B-F, P3B-F (both of which
which I haven't touched), and my under-development P2B-LS targets and they
all fail.

I need to figure out why romcc won't compile this. I wrote some stubs that I
use to test this code under userspace with dummy SPD dumps from a dozen of
my DIMM modules. I define TESTJIG when I'm compiling raminit.c to use these
stubs for my own userspace testing. gcc is used to compile both my stubs and
raminit.c for those tests and they all compile and seems to run fine. Now I
need to boot test it.

This code needs some expansion for i440bx because it supports a number of
features not present in i830.

Below are output of make when I tried to compile:

ramtest.c:6.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
ramtest.c:56.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
raminit.c:605.46: raminit.c:789.32: romstage.c:96.32:
0xd28680 or         Internal compiler error: non dominated rhs use point
0xd288d0?
make: *** [/usr/src/coreboot/build/mainboard/asus/p2b-ls/romstage.inc]
Aborted

The part of raminit.c that croaks is:

...
            if (value == SPD_MEMORY_TYPE_EDO) {
                edosd |= 0x02;
                PRINT_DEBUG("EDO");
            } else if (value == SPD_MEMORY_TYPE_SDRAM) {
                edosd |= 0x04;  // <<< ABORT!
                PRINT_DEBUG("SDRAM");   // <<< ABORT!
            }
...

Let me add another few questions here. I want to add code to have coreboot
talk to the clock chip to find out its FSB in order to select the fastest
memory timing from SPD data. 440BX only has official support for 100MHz, but
they often are taken to 133MHz and beyond - my two boards are tested stable
to 140MHz. I know the clock chip sits on SMBus, and have a fixed address at
0x69. That's with the clock chip my board uses. Where should this code be
placed?

The vendor BIOS placed the PIIX4E power management device base port at
0xE400, and its SMBus base port at 0xE800. Coreboot has its SMBus base port
at 0x0F00. If I want to change the base port to match vendor BIOS, where
should it be made?

Any help appreciated.

Thanks
Keith

[Joseph Smith]

On Tue, 2 Mar 2010 00:39:12 -0500, Keith Hui  wrote:
> ramtest.c:6.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
> ramtest.c:56.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
> raminit.c:605.46: raminit.c:789.32: romstage.c:96.32:
> 0xd28680 or         Internal compiler error: non dominated rhs use point
> 0xd288d0?
> make: *** [/usr/src/coreboot/build/mainboard/asus/p2b-ls/romstage.inc]
> Aborted

That is a very strange message, sorry I have never seen that before.
> The part of raminit.c that croaks is:
>
> ...
>             if (value == SPD_MEMORY_TYPE_EDO) {
>                 edosd |= 0x02;
>                 PRINT_DEBUG("EDO");
>             } else if (value == SPD_MEMORY_TYPE_SDRAM) {
>                 edosd |= 0x04;  // <<< ABORT!
>                 PRINT_DEBUG("SDRAM");   // <<< ABORT!
>             }
> ...

Hmm, this looks fine.

HELP: Porting i830 RAM init to 440BX, now it won't compile

[ron minnich]

On Tue, Mar 2, 2010 at 5:39 AM, Keith Hui  wrote:
> ramtest.c:6.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
> ramtest.c:56.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0

fix this first. You really want your code to be warning-free.
> edosd |= 0x04;  // <<< ABORT!

did you try just edosd = edosd | 4;

just wondering if it's that simple.
> That's with the clock chip my board uses. Where should this code be
> placed?

depends on the chip I assume. Very, very early is my bet.
> The vendor BIOS placed the PIIX4E power management device base port at
> 0xE400, and its SMBus base port at 0xE800. Coreboot has its SMBus base port
> at 0x0F00. If I want to change the base port to match vendor BIOS, where
> should it be made?

Why? We've never seen a need to match these addresses up.

ron

HELP: Porting i830 RAM init to 440BX, now it won't compile

[Keith Hui]

On Tue, Mar 2, 2010 at 11:22 AM, ron minnich  wrote:
> On Tue, Mar 2, 2010 at 5:39 AM, Keith Hui  wrote:
> > ramtest.c:6.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
> > ramtest.c:56.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
>
> fix this first. You really want your code to be warning-free.
>
> I did a search, and the only reference (ie. this ramtest.c) is elsewhere in

the code - src/lib/. That may be used by something else.
> >             edosd |= 0x04;  // <<< ABORT!
>
> did you try just edosd = edosd | 4;
>
> just wondering if it's that simple.
>
> I could try tonight. But I used both notations fearing that romcc doesn't

support more obscure constructs, and both work in other places.
> > That's with the clock chip my board uses. Where should this code be
> > placed?
>
> depends on the chip I assume. Very, very early is my bet.
>
> I'm mean where in the source tree should I put it. Southbridge,

mainboard-specific romstage, or northbridge?
> > The vendor BIOS placed the PIIX4E power management device base port at
> > 0xE400, and its SMBus base port at 0xE800. Coreboot has its SMBus base
>
> port
> > at 0x0F00. If I want to change the base port to match vendor BIOS, where
> > should it be made?
>
> Why? We've never seen a need to match these addresses up.
>
> So that when I disassemble my coreboot image, I can look at it side by side

with vendor BIOS and check that it's doing the right thing.

I also don't know if there's anything else in the 0x0F00 port range.

This may also become an issue when the ACPI tables in vendor BIOS gets
carried over here and actually gets wired up.

Thanks
Keith

HELP: Porting i830 RAM init to 440BX, now it won't compile

[Joseph Smith]

On Tue, 2 Mar 2010 11:43:42 -0500, Keith Hui  wrote:
> On Tue, Mar 2, 2010 at 11:22 AM, ron minnich  wrote:
> > On Tue, Mar 2, 2010 at 5:39 AM, Keith Hui  wrote:
> > > ramtest.c:6.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
> > > ramtest.c:56.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0

This should be fixed in Kconfig. Probibly in the cpu Kconfig?
> > fix this first. You really want your code to be warning-free.
> >
> > I did a search, and the only reference (ie. this ramtest.c) is elsewhere
>
> in
> the code - src/lib/. That may be used by something else.
> > >             edosd |= 0x04;  // <<< ABORT!
> >
> > did you try just edosd = edosd | 4;
> >
> > just wondering if it's that simple.
> >
> > I could try tonight. But I used both notations fearing that romcc

doesn't
> support more obscure constructs, and both work in other places.

hmm
> > > That's with the clock chip my board uses. Where should this code be
> > > placed?
> >
> > depends on the chip I assume. Very, very early is my bet.
> >
> > I'm mean where in the source tree should I put it. Southbridge,
>
> mainboard-specific romstage, or northbridge?

I would say romstage.c just after early_smbus runs.
> > > The vendor BIOS placed the PIIX4E power management device base port at
> > > 0xE400, and its SMBus base port at 0xE800. Coreboot has its SMBus base
> >
> > port
> > > at 0x0F00. If I want to change the base port to match vendor BIOS,
>
> where
> > > should it be made?
> >
> > Why? We've never seen a need to match these addresses up.
> >
> > So that when I disassemble my coreboot image, I can look at it side by
>
> side
> with vendor BIOS and check that it's doing the right thing.
>
> I also don't know if there's anything else in the 0x0F00 port range.
>
> This may also become an issue when the ACPI tables in vendor BIOS gets
> carried over here and actually gets wired up.

I wouldn't worry to much about ACPI now. You have a ways to go before you
get to that point.

HELP: Porting i830 RAM init to 440BX, now it won't compile

[Keith Hui]

On Tue, Mar 2, 2010 at 12:53 PM, Joseph Smith  wrote:
> On Tue, 2 Mar 2010 11:43:42 -0500, Keith Hui  wrote:
> > On Tue, Mar 2, 2010 at 11:22 AM, ron minnich  wrote:
> > > On Tue, Mar 2, 2010 at 5:39 AM, Keith Hui  wrote:
> > > > ramtest.c:6.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
> > > > ramtest.c:56.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
>
> This should be fixed in Kconfig. Probibly in the cpu Kconfig?
> > > fix this first. You really want your code to be warning-free.
> > >
> > > I did a search, and the only reference (ie. this ramtest.c) is elsewhere
> >
> > in
> > the code - src/lib/. That may be used by something else.
> > > >             edosd |= 0x04;  // <<< ABORT!
> > >
> > > did you try just edosd = edosd | 4;
> > >
> > > just wondering if it's that simple.
> > >
> > > I could try tonight. But I used both notations fearing that romcc
>
> doesn't
> > support more obscure constructs, and both work in other places.
>
> hmm

I did it - I made the above change (though I doubt it made any difference)
and have to remove the PRINT_DEBUG mentioned in my original email for it to
compile.

Time to boot test.

* Clacks away *

This is the biggest excitement after Canada winning Hockey Gold at the
winter Olympics! (see attached log)

I have 256MB and Linux boots to the login prompt!

I'll formulate a patch later adding this and P2B-LS support.

Cheers
Keith

[Joseph Smith]

> I did it - I made the above change (though I doubt it made any

difference)
> and have to remove the PRINT_DEBUG mentioned in my original email for it

to
> compile.
>
> Time to boot test.
> Clacks away *
>
> This is the biggest excitement after Canada winning Hockey Gold at the
> winter Olympics! (see attached log)
>
> I have 256MB and Linux boots to the login prompt!
>
> I'll formulate a patch later adding this and P2B-LS support.

That's great! Congrats :-)

HELP: Porting i830 RAM init to 440BX, now it won't compile

[ron minnich]

Keith, Nice job!

I will have to disagree with you about the hockey results though :-)

ron

HELP: Porting i830 RAM init to 440BX, now it won't compile

[ron minnich]

On Tue, Mar 2, 2010 at 8:43 AM, Keith Hui  wrote:
> I'm mean where in the source tree should I put it. Southbridge,
> mainboard-specific romstage, or northbridge?

mainboard. Whether overclocking works, and how well it works, is very
specific to a given mainboard.

ron