Re: [LinuxBIOS] RAM organization - can 8 16Mbx16 chips give a single-rank 32Mbx64 DIMM?

[Lu, Yinghai]

You can read the SPD ROM data on other Machine. And then check the value
according the DDR spd sepc.

YH

-----Original Message-----
From: [e-mail]
[mailto:[e-mail]] On Behalf Of Miernik
Sent: Sunday, March 05, 2006 11:52 PM
To: [e-mail]
Subject: [LinuxBIOS] RAM organization - can 8 16Mbx16 chips give a
single-rank 32Mbx64 DIMM?

I have a DDR266 SO-DIMM module with 8 chips on it. I only know the specs
on the chips, they are 16Mb x 16 organization. I don't know the specs of
the whole module, there isn't even a model number.

I want to know the organization of the whole module.
Is it a dual-rank ("double-sided") module with 16Mb x 64 in each rank?
Or is it a single-rank ("single-sided") module with 32Mb x 64
organization?

Is the latter at all possible?
If yes, how to tell the difference by looking at the module?

The reason I ask, is that
http://transmeta.com/crusoe_docs/TM5800v1.0_DataBook_030206.pdf
on page 19 states that the memory controller supports only 1 rank with
DDR. That limitation doesn't apply to SDR controller or to DDR
controller on version 2.1 chips - page 21 on
http://transmeta.com/crusoe_docs/TM5800v2.1_databook_030922.pdf

I have a 5800A073310 chip, and I would like to know if that DDR module
should work with it or not. And also will a 1 GB DDR module work with
it. With v1.0 documentation it appears that not, but with v2.1 on page
23 it lists a 1024 MB DDR configuration with two ranks, is it possible
that v1.0 will somehow support it, only the docs didn't list it?

The module in question is here:
http://217.17.47.111/items/SMART_TM2V16M1618U-4/SMART_TM2V16M1618U-4.fro
nt.jpeg
http://217.17.47.111/items/SMART_TM2V16M1618U-4/SMART_TM2V16M1618U-4.bac
k.jpeg