Hi,
given the lack of affordable and available hardware tools for coreboot development, I propose to look for a different set of projects this year: Tools which would help developers, and which are usable especially with current hardware. A list of ideas follows.
- Flash ICE device with SPI support. - Flash ICE device with LPC/FWH support. - Serial emulation for LPC buses on a configurable I/O port with USB output on the other side. - Dual serial emulation for two LPC buses either on the same device or with two identical devices and a fast bus in between. - Serial emulation for PCI buses (i.e. PCI/serial card).
The reason for the flash ICE devices is obvious: Avoid external reflashing while you're developing.
The serial emulation or similar POST code port emulation is meant to provide a serial console, a SerialICE connection and/or some POST code output channel. This is especially important for laptops where debugging can be a pain and where you usually have a LPC bus available in the MiniPCIe slot.
The dual serial emulation for two LPC buses would work as a fast PC-to-PC connection for SerialICE and other purposes where you need low latency, not necessarily high throughput.
The serial emulation for PCI buses would complement the serial emulation for LPC to provide an easy way to connect to a SerialICE instance on the other side.
As a basis for all those ideas I'd propose the Openbench logic sniffer. It has a fast FPGA, enough gates and roughly 32 kByte RAM. The FPGA is fast enough and big enough to accommodate the necessary logic, and we could easily attach a fast (66+ MHz) SPI flash chip to it. And with $50 incl. shipping the OLS is not extremely cheap, but worth its price and easily available. Fast flash chips are also available for reasonable prices.
All of those projects would not result in any coreboot code, but they would make development easier, and that's a value in itself, especially now that we're porting coreboot to laptops where a LPC bus may be the only easily available bus at startup.
Comments? Do we have mentors who can review VHDL/Verilog?
Regards, Carl-Daniel
On 03/10/2012 02:27 PM, Carl-Daniel Hailfinger wrote:
Do we have mentors who can review VHDL/Verilog?
I could help with that.
BTW an open hardware AMD Fusion card is being spun in the EOMA68 form factor for notebooks/netbooks/tablets etc in addition to the open ARM modules. http://elinux.org/Embedded_Open_Modular_Architecture/EOMA-68 http://rhombus-tech.net./amd_g_series/ This will make things easier since the modules will only come with coreboot plus open firmware for the 32b ARM EC.
-Bari
Hi Carl-Daniel,
I don't qualify as GSoC student (too old ;) ). For sure I can't be mentor because I am absolute newbie here, but I am interested to find out If I can help with one of those projects. I know the theory how those things are working, but I have zero experience. Do you think I can be useful even if it is outside the GSoC program?
Thanks, Svetoslav Trochev
On Sat, Mar 10, 2012 at 12:27 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
Hi,
given the lack of affordable and available hardware tools for coreboot development, I propose to look for a different set of projects this year: Tools which would help developers, and which are usable especially with current hardware. A list of ideas follows.
- Flash ICE device with SPI support.
- Flash ICE device with LPC/FWH support.
- Serial emulation for LPC buses on a configurable I/O port with USB
output on the other side.
- Dual serial emulation for two LPC buses either on the same device or
with two identical devices and a fast bus in between.
- Serial emulation for PCI buses (i.e. PCI/serial card).
The reason for the flash ICE devices is obvious: Avoid external reflashing while you're developing.
The serial emulation or similar POST code port emulation is meant to provide a serial console, a SerialICE connection and/or some POST code output channel. This is especially important for laptops where debugging can be a pain and where you usually have a LPC bus available in the MiniPCIe slot.
The dual serial emulation for two LPC buses would work as a fast PC-to-PC connection for SerialICE and other purposes where you need low latency, not necessarily high throughput.
The serial emulation for PCI buses would complement the serial emulation for LPC to provide an easy way to connect to a SerialICE instance on the other side.
As a basis for all those ideas I'd propose the Openbench logic sniffer. It has a fast FPGA, enough gates and roughly 32 kByte RAM. The FPGA is fast enough and big enough to accommodate the necessary logic, and we could easily attach a fast (66+ MHz) SPI flash chip to it. And with $50 incl. shipping the OLS is not extremely cheap, but worth its price and easily available. Fast flash chips are also available for reasonable prices.
All of those projects would not result in any coreboot code, but they would make development easier, and that's a value in itself, especially now that we're porting coreboot to laptops where a LPC bus may be the only easily available bus at startup.
Comments? Do we have mentors who can review VHDL/Verilog?
Regards, Carl-Daniel
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Carl-Daniel Hailfinger wrote:
Tools which would help developers, usable .. with current hardware.
I think the best way is to put them on the Talk:GSoC wiki page. Ie. not on the GSoC page itself, but on the discussion page for that page.
- Flash ICE device with SPI support.
- Flash ICE device with LPC/FWH support.
- Serial emulation for LPC buses on a configurable I/O port with
USB output on the other side.
Sure. If there are students with a hardware interest I think these are good projects. There is also much VHDL available already.
As a basis for all those ideas I'd propose the Openbench logic sniffer.
Yes and no. OLS is fine as a prototyping and development platform for these projects, but it's an incredibly poor design when it comes to USB, and it doesn't fit in the expansion slot.
It has a fast FPGA, enough gates and roughly 32 kByte RAM.
The RAM is block RAM inside the FPGA, which can not be arbitrarily used from logic. The OLS doesn't have a separate RAM chip. One needs to be connected externally. It's not impossible, but requires some soldering skill.
we could easily attach a fast (66+ MHz) SPI flash chip to it.
The OLS as SPI master mux for having an easy way to flash a real chip used by a mainboard when booting is fine. But the chip should be able to reside on the mainboard, and the OLS should drive the mainboard reset while flashing. Having the OLS connect via wires means that the SPI flash can not be driven quite so fast. The shorter wires the better. The OLS is a big board with exposed contacts on the bottom.
The OLS is not a good fit for installation into e.g. a laptop. This is one of the use cases for a QiProg; it's intended to be soldered into the target system, on top of, or very near, the flash chip.
All of those projects would not result in any coreboot code, but they would make development easier,
I think this is fine, and we've had similar project ideas already. Also some of our previous running projects have resulted in code outside of coreboot but which complements coreboot significantly. Assisting development counts too.
now that we're porting coreboot to laptops where a LPC bus may be the only easily available bus at startup.
I don't know that LPC is usually available, but even so it is a nice start, and VHDL already exists.
Do we have mentors who can review VHDL/Verilog?
Yes.
//Peter
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Bari Ari -
Carl-Daniel Hailfinger -
Peter Stuge -
Svetoslav Trochev