More could be done to open up a larger ROM area etc but this will inform you of a major problem.
Marc
On Tue, Oct 14, 2008 at 5:22 PM, Marc Jones Marc.Jones@amd.com wrote:
More could be done to open up a larger ROM area etc but this will inform you of a major problem.
bummer!
Acked-by: Ronald G. Minnich rminnich@gmail.com
no workaround in the bios setup? I guess I will see.
ron
[root@amd64 flashrom]# ./flashrom -w /tmp/bios.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "ATI(AMD) SB600", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED! [root@amd64 flashrom]#
Marc, you had no trouble right? This is odd.
ron
ron minnich wrote:
Found chipset "ATI(AMD) SB600", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED!
..
Marc, you had no trouble right? This is odd.
Identical hardware and BIOS?
Which voltage do you have on pin 7 and 8 of the flash chip?
And doesn't this guy have block lock registers? (It's using the sst_fwhub driver, which doesn't know about lock registers.)
//Peter
On Tue, Oct 14, 2008 at 8:14 PM, Peter Stuge peter@stuge.se wrote:
ron minnich wrote:
Found chipset "ATI(AMD) SB600", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED!
..
Marc, you had no trouble right? This is odd.
Identical hardware and BIOS?
Which voltage do you have on pin 7 and 8 of the flash chip?
And doesn't this guy have block lock registers? (It's using the sst_fwhub driver, which doesn't know about lock registers.)
what's odd is it won't for either the lpc or fwhub versions of the part. the 080a is in there, and fails, The 004b fails too. Which one of these is fwh? 004?
ron
ron minnich wrote:
Which voltage do you have on pin 7 and 8 of the flash chip?
Can you check this?
And doesn't this guy have block lock registers? (It's using the sst_fwhub driver, which doesn't know about lock registers.)
what's odd is it won't for either the lpc or fwhub versions of the part. the 080a is in there, and fails, The 004b fails too. Which one of these is fwh? 004?
Yes. 080 uses sst49lf040 driver which also doesn't look at blocks.
Try using the _49fl00x functions.
//Peter
ron minnich wrote:
[root@amd64 flashrom]# ./flashrom -w /tmp/bios.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "ATI(AMD) SB600", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED! [root@amd64 flashrom]#
Marc, you had no trouble right? This is odd.
This is with my patch? Please send lspci.
The chipset isn't detected but my system can read/write/erase ok. I don't know if your BIOS is write protecting the ROM. Can you dump the lpc bridge registers?
$ lspci -s 0:0:14.3 -xxx
Marc
On Wed, Oct 15, 2008 at 8:58 AM, Marc Jones Marc.Jones@amd.com wrote:
This is with my patch?
yes
Please send lspci.
00:14.3 ISA bridge: ATI Technologies Inc SB600 PCI to LPC Bridge 00: 02 10 8d 43 0f 00 20 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 8d 43 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 04 00 00 00 43 c0 c3 f7 17 ff 42 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 0e 00 00 0e 00 0f 00 f0 ff ff ff 70: 67 45 23 01 00 00 00 00 01 00 00 00 05 00 00 00 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 01 c0 fe 00 00 00 00 00 00 00 00 00 00 00 00 b0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ron minnich wrote:
On Wed, Oct 15, 2008 at 8:58 AM, Marc Jones Marc.Jones@amd.com wrote:
This is with my patch?
yes
Please send lspci.
00:14.3 ISA bridge: ATI Technologies Inc SB600 PCI to LPC Bridge 00: 02 10 8d 43 0f 00 20 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 8d 43 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 04 00 00 00 43 c0 c3 f7 17 ff 42 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 0e 00 00 0e 00 0f 00 f0 ff ff ff 70: 67 45 23 01 00 00 00 00 01 00 00 00 05 00 00 00 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 01 c0 fe 00 00 00 00 00 00 00 00 00 00 00 00 b0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
That looks identical to my system. There isn't a write protect set and the decode is 1MB. I used a sst49lf080a without issue.
Marc
Marc Jones wrote:
SB600 has four write once LPC ROM protect areas. It is not possible to write enable that area once the register is set so print a warning.
Signed-off-by: Marc Jones marcj.jones@amd.com
Clean up the whitespace before committing please.
Acked-by: Peter Stuge peter@stuge.se
Peter Stuge wrote:
Marc Jones wrote:
SB600 has four write once LPC ROM protect areas. It is not possible to write enable that area once the register is set so print a warning.
Signed-off-by: Marc Jones marcj.jones@amd.com
Clean up the whitespace before committing please.
done
Acked-by: Peter Stuge peter@stuge.se
r3659 Thanks, Marc
On 15.10.2008 02:22, Marc Jones wrote:
More could be done to open up a larger ROM area etc but this will inform you of a major problem.
SB600 has four write once LPC ROM protect areas. It is not possible to write enable that area once the register is set so print a warning.
Signed-off-by: Marc Jones marcj.jones@amd.com
Good initial implementation. We may want to support SB600 SPI later.
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Regards, Carl-Daniel
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Carl-Daniel Hailfinger -
Marc Jones -
Peter Stuge -
ron minnich