[patch][v2] AMD fam10 rev B3 memory init

[Marc Jones]

Add memory init support for B3.

Marc

[Carl-Daniel Hailfinger]

On 22.07.2008 01:02, Marc Jones wrote:
> Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).
>
> Signed-off-by: Marc Jones
> Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
>
> --- coreboot-v2.orig/src/northbridge/amd/amdmct/mct/mct_d.c	2008-07-21 15:40:02.000000000 -0600
> +++ coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c	2008-07-21 16:14:22.000000000 -0600
> @@ -2401,30 +2401,34 @@
>    mct_BeforeDramInit_Prod_D(pMCTstat, pDCTstat);
>    // FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct);
> /* Disable auto refresh before Dram init when in ganged mode */
> if (pDCTstat->GangedMode) {
> val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
> val |= 1 << DisAutoRefresh;
> Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val);
> /* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */
> if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) {

This is a behaviour change for B2. Before, the code path was taken for
B2, now it isn't anymore.

src/northbridge/amd/amdmct/amddefs.h has some nice CPUID combiners like
AMD_DR_LT_B3. Maybe you can use one of them.
> if (pDCTstat->GangedMode) {
> 	val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
> 	val |= 1 << DisAutoRefresh;
> 	Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val);
> }
>
> }
>
> mct_DramInit_Hw_D(pMCTstat, pDCTstat, dct);
>
> /* Re-enable auto refresh after Dram init when in ganged mode
> * to ensure both DCTs are in sync
> * to ensure both DCTs are in sync (Erratum 278)
> */
> if (pDCTstat->GangedMode) {
> do {
> 	val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));
> } while (!(val & (1 << InitDram)));
> WaitRoutine_D(50);
> val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
> val &= ~(1 << DisAutoRefresh);
> val |= 1 << DisAutoRefresh;
> val &= ~(1 << DisAutoRefresh);
> if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) {

Same comments as above.
> if (pDCTstat->GangedMode) {
> 	do {
> 		val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));
> 	} while (!(val & (1 << InitDram)));
> 	WaitRoutine_D(50);
> 	val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
> 	val &= ~(1 << DisAutoRefresh);
> 	val |= 1 << DisAutoRefresh;
> 	val &= ~(1 << DisAutoRefresh);
> }
> }
>
> }
>
> @@ -3792,7 +3796,10 @@
>    u8 wrap32dis = 0;
>    u8 valid = 0;
> /* FIXME: Skip reset DLL for B3 */
>
> /* Skip reset DLL for B3 */
>
> if (pDCTstat->LogicalCPUID & AMD_DR_B3) {
> return;
>
> }
>
> addr = HWCR;
> _RDMSR(addr, &lo, &hi);
>
> @@ -3885,8 +3892,7 @@
>    u32 reg_off = 0x100 * dct;
>    u32 dev = pDCTstat->dev_dct;
> /* FIXME: Add B3 */
> if (pDCTstat->LogicalCPUID & AMD_DR_B2) {
> if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) {
> mct_Wait(10000);	/* Wait 50 us*/
> val = Get_NB32(dev, 0x110);
> if ( val & (1 << DramEnabled)) {

With the points above addressed, the patch is
Acked-by: Carl-Daniel Hailfinger

Regards,
Carl_Daniel

[Marc Jones]

Carl-Daniel Hailfinger wrote:
> On 22.07.2008 01:02, Marc Jones wrote:
> > Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).
> >
> > Signed-off-by: Marc Jones
> > Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
> >
> > --- coreboot-v2.orig/src/northbridge/amd/amdmct/mct/mct_d.c	2008-07-21 15:40:02.000000000 -0600
> > +++ coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c	2008-07-21 16:14:22.000000000 -0600
> > @@ -2401,30 +2401,34 @@
> >    mct_BeforeDramInit_Prod_D(pMCTstat, pDCTstat);
> >    // FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct);
> > /* Disable auto refresh before Dram init when in ganged mode */
> > if (pDCTstat->GangedMode) {
> > val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
> > val |= 1 << DisAutoRefresh;
> > Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val);
> > /* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */
> > if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) {
>
> This is a behaviour change for B2. Before, the code path was taken for
> B2, now it isn't anymore.

I don't know if this was missed in the for B2 or if the errata changed. 
Anyway, skip the setting less than B2.
> src/northbridge/amd/amdmct/amddefs.h has some nice CPUID combiners like
> AMD_DR_LT_B3. Maybe you can use one of them.

I added a AMD_DR_LT_B2 define.
> With the points above addressed, the patch is
> Acked-by: Carl-Daniel Hailfinger

r3433

Thanks,
Marc