how to route IRQ4 (COM1) on LPC bus for bayleybay_fsp

[benoit]

Hi all,

I am currently running coreboot + fsp on a E3837 cpu based platform.
My platform has serial line in a LPC device.
Firstly, I activated the SERIRQ in continous mode.
Nevertheless under operating system, the IRQ4 for COM1 is not available.

I checked out the file  src/mainboard/intel/bayleybay_fsp/irqtable.h
And I saw that for the LPC interface :

PCI_DEV_PIRQ_ROUTE(PCU_DEV,     H, G, B, C)
...
#define PIRQ_PIC_ROUTES \
    PIRQ_PIC(A,  4), \
    PIRQ_PIC(B,  5), \
    PIRQ_PIC(C,  7), \
    PIRQ_PIC(D, 10), \
    PIRQ_PIC(E, 11), \
    PIRQ_PIC(F, 12), \
    PIRQ_PIC(G, 14), \
    PIRQ_PIC(H, 15)

I know that this configuration is available from the ILB_BASE_ADDRESS
(0xfed08000).
But I don't really understand, how to route the IRQ4 from LPC dev.

Is someone can explain to me how to do it properly?

Many thanks in advance
Benoit

[Rudolf Marek]

Hi

What does it mean not available? Maybe you can check if you programmed ELCR
register to edge for IRQ4.

You can't share the IRQ4 with PCI IRQ I think thats why it does not work.

You need to route the the PIRQA to something else, like IRQ3.

Thanks
Rudolf

[benoit]

Hi

I mean by not available : not working under my real time OS that I load
through a grub2 paylaod.

You are right.
I replace the IRQ 4 by an other one that it is not used in my system as
follow :

#define PIRQ_PIC_ROUTES \
        PIRQ_PIC(A,  5), \
        PIRQ_PIC(B,  6), \
        PIRQ_PIC(C,  7), \
        PIRQ_PIC(D, 10), \
        PIRQ_PIC(E, 11), \
        PIRQ_PIC(F, 12), \
        PIRQ_PIC(G, 14), \
        PIRQ_PIC(H, 15)

And it works. Perfectly.
I have my serial console on COM1 under the OS.
I did not chose IRQ 3 because I am using also the COM2.

Many thanks
Benoit

On 14/01/2016 23:02, Rudolf Marek wrote:
> Hi
>
> What does it mean not available? Maybe you can check if you programmed ELCR
> register to edge for IRQ4.
>
> You can't share the IRQ4 with PCI IRQ I think thats why it does not work.
>
> You need to route the the PIRQA to something else, like IRQ3.
>
> Thanks
> Rudolf
> .

[Aaron Durbin]

On Tue, Jan 12, 2016 at 2:32 PM, benoit  wrote:
> Hi all,
>
> I am currently running coreboot + fsp on a E3837 cpu based platform.
> My platform has serial line in a LPC device.
> Firstly, I activated the SERIRQ in continous mode.

SERIRQ has nothing to do w/ COM1. SERIRQ is pulled in on LPC.
> Nevertheless under operating system, the IRQ4 for COM1 is not available.

IRQEN (IRQE)—Offset 88h bit 4 indicates UART IRQ4 Enable. The
datasheet says RO, but you could double check that it's RW. That sit
behind the ILB_BASE_ADDRESS.

In the datasheet it's section 34.3.53.
http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e380...
> I checked out the file  src/mainboard/intel/bayleybay_fsp/irqtable.h
> And I saw that for the LPC interface :
>
> PCI_DEV_PIRQ_ROUTE(PCU_DEV,     H, G, B, C)
> ...
> #define PIRQ_PIC_ROUTES \
>         PIRQ_PIC(A,  4), \
>         PIRQ_PIC(B,  5), \
>         PIRQ_PIC(C,  7), \
>         PIRQ_PIC(D, 10), \
>         PIRQ_PIC(E, 11), \
>         PIRQ_PIC(F, 12), \
>         PIRQ_PIC(G, 14), \
>         PIRQ_PIC(H, 15)
>
> I know that this configuration is available from the ILB_BASE_ADDRESS
> (0xfed08000).
> But I don't really understand, how to route the IRQ4 from LPC dev.
>
> Is someone can explain to me how to do it properly?
>
> Many thanks in advance
> Benoit