On Saturday, March 22, 2014 03:56:46 AM Andrew Wu wrote:
Yes, that is right. DMP/Vortex86EX has no MTRR. So it maybe a problem if without romcc. :(
Is there any way whatsoever to temporarily use the cache as SRAM?
Alex
On Fri, Mar 21, 2014 at 1:33 PM, mrnuke mr.nuke.me@gmail.com wrote:
On Saturday, March 22, 2014 03:56:46 AM Andrew Wu wrote:
Yes, that is right. DMP/Vortex86EX has no MTRR. So it maybe a problem if without romcc. :(
Is there any way whatsoever to temporarily use the cache as SRAM?
when we did the first real CAR work MTRRs were not needed. I'm not sure if they would be on the vortex. We might want to test the very early CAR code and see how it goes. It's actually quite simple.
Also, let's just take it a little easy here. These are proposals, nothing is ever perfect on first release, the world is not ending, Google is not showing up at coreboot.org in skimasks and unmarked uniforms ...
I think a fork would harm everyone, and would be destructive of our common goals. Please remember that we are all trying to do the right thing, and our different situations give us different perspectives.
Nobody is coming in here with bad motives. We're just trying to muddle our way through the many demands of different stakeholders now that coreboot, thanks to the efforts of some pretty dedicated people, has become a runaway success.
ron
2014-03-22 4:33 GMT+08:00 mrnuke mr.nuke.me@gmail.com:
On Saturday, March 22, 2014 03:56:46 AM Andrew Wu wrote:
Yes, that is right. DMP/Vortex86EX has no MTRR. So it maybe a problem if without romcc. :(
Is there any way whatsoever to temporarily use the cache as SRAM?
Alex
Sorry, I checked Vortex86EX CPU datasheet, but it seems there is no workaround can do it.
So if I want to get rid of romcc, maybe I have to write DRAM init code in assembly, That is not very easy. :(
Andrew