4 GB RAM failure on DBM690T target (690G/SB600)

[Carl-Daniel Hailfinger]

Hi,

I'm using a slightly modified DBM690T target to boot my Asus M2A-VM
(690G/SB600) board.

Booting with 4 GB RAM (2x2) into Linux fails with lots of ACPI errors
because the ACPI code for DBM690T hardcodes 1 GB of RAM and has the code
paths for >4 GB commented out.

My attempts to fix this have been unsuccessful.

Was the DBM690T ever tested with 4 GB RAM and did it boot into Linux?

Regards,
Carl-Daniel

[Marc Jones]

On Fri, Jan 16, 2009 at 10:36 AM, Carl-Daniel Hailfinger
 wrote:
> Hi,
>
> I'm using a slightly modified DBM690T target to boot my Asus M2A-VM
> (690G/SB600) board.
>
> Booting with 4 GB RAM (2x2) into Linux fails with lots of ACPI errors
> because the ACPI code for DBM690T hardcodes 1 GB of RAM and has the code
> paths for >4 GB commented out.
>
> My attempts to fix this have been unsuccessful.
>
> Was the DBM690T ever tested with 4 GB RAM and did it boot into Linux?

No, It was not tested with that much RAM. The main reason is that it
uses SoDIMMs and is meant for amobile package which would not need >
4GB. I am suprised to hear that the ACPI code is hard coded to 1GB. It
shouldn't be that hard to check TOM and TOM2 to put that information
into the tables. What is the exact failure?

Marc

[Carl-Daniel Hailfinger]

On 17.01.2009 18:03, Marc Jones wrote:
> On Fri, Jan 16, 2009 at 10:36 AM, Carl-Daniel Hailfinger
>  wrote:
> > Hi,
> >
> > I'm using a slightly modified DBM690T target to boot my Asus M2A-VM
> > (690G/SB600) board.
> >
> > Booting with 4 GB RAM (2x2) into Linux fails with lots of ACPI errors
> > because the ACPI code for DBM690T hardcodes 1 GB of RAM and has the code
> > paths for >4 GB commented out.
> >
> > My attempts to fix this have been unsuccessful.
> >
> > Was the DBM690T ever tested with 4 GB RAM and did it boot into Linux?
>
> No, It was not tested with that much RAM. The main reason is that it
> uses SoDIMMs and is meant for amobile package which would not need >
> 4GB.

2x2 GB DDR2 SODIMMs can be bought for a total of ~$50 now*
http://tinyurl.com/2x2gb-ddr2-800-sodimm* , so I believe we will see
embedded deployments with 4 GB RAM soon.
Unless I am misreading the ACPI code, the code path for >3 GB is disabled.
> I am suprised to hear that the ACPI code is hard coded to 1GB. It
> shouldn't be that hard to check TOM and TOM2 to put that information
> into the tables.

I'm not totally sure the ACPI code is hard coded to 1 GB. The default
values in the ACPI code code correspond to 1 GB and there is some code
which will calculate BIOS memory location from TOM and TOM2. I could not
find any place where TOM and TOM2 are updated, though. And the ACPI code
to handle nonzero TOM2 is disabled (when I tried to enable it, the ACPI
compiler complained that stuffing 64bit values into 32bit fields is not
allowed).
> What is the exact failure?

Lots of these:
ACPI Error (exregion-0164): Could not map memory at 0000000100000128,
size ED7 [20070126]
ACPI Exception (evregion-0420): AE_NO_MEMORY, Returned by Handler for
[SystemMemory] [20070126]
ACPI Exception (dswexec-0462): AE_NO_MEMORY, While resolving operands
for [LGreater] [20070126]
ACPI Error (psparse-0537): Method parse/execution failed
[_SB_.PCI0.STCR.PMRY.PMST._STA] (Node ffff81013fa524f0), AE_NO_MEMORY

Full boot log is attached.

[Rudolf Marek]

> I'm not totally sure the ACPI code is hard coded to 1 GB. The default
> values in the ACPI code code correspond to 1 GB and there is some code
> which will calculate BIOS memory location from TOM and TOM2. I could not
> find any place where TOM and TOM2 are updated,

its in acpi-k8.c in amd directory. Its in ssdt table.

Rudolf

[Carl-Daniel Hailfinger]

On 20.01.2009 17:13, Rudolf Marek wrote:
> > I'm not totally sure the ACPI code is hard coded to 1 GB. The default
> > values in the ACPI code code correspond to 1 GB and there is some code
> > which will calculate BIOS memory location from TOM and TOM2. I could not
> > find any place where TOM and TOM2 are updated,
>
> its in acpi-k8.c in amd directory. Its in ssdt table.

Thanks. Unfortunately, the situation is more complicated on DBM690T.
TOM (the top below 4 GB) is stored twice, once in the SSDT (modified
automatically) and once in the DSDT (unmodified). TOM2 is only stored in
the DSDT (unmodified). The (correct) value of TOM in the SSDT is ignored
and the (incorrect) values of TOM/TOM2 in the DSDT are used.

Regards,
Carl-Daniel

[Marc Jones]

On Tue, Jan 20, 2009 at 6:50 PM, Carl-Daniel Hailfinger
 wrote:
> On 20.01.2009 17:13, Rudolf Marek wrote:
> > > I'm not totally sure the ACPI code is hard coded to 1 GB. The default
> > > values in the ACPI code code correspond to 1 GB and there is some code
> > > which will calculate BIOS memory location from TOM and TOM2. I could not
> > > find any place where TOM and TOM2 are updated,
> >
> > its in acpi-k8.c in amd directory. Its in ssdt table.
>
> Thanks. Unfortunately, the situation is more complicated on DBM690T.
> TOM (the top below 4 GB) is stored twice, once in the SSDT (modified
> automatically) and once in the DSDT (unmodified). TOM2 is only stored in
> the DSDT (unmodified). The (correct) value of TOM in the SSDT is ignored
> and the (incorrect) values of TOM/TOM2 in the DSDT are used.

This sounds like a oversite. Maybe the AMD BTDC guys can help.
Marc

[Bao, Zheng]

We will try to debug this after the Chinese New Year.

Now I am debugging the shiner (RS780/SB700). The board will be returned
in a week, so I have to focus on this. Now most of the feature is
working, except VGA.

Zheng

-----Original Message-----
From: Marc Jones [mailto:[e-mail]] 
Sent: Wednesday, January 21, 2009 9:58 AM
To: Carl-Daniel Hailfinger
Cc: Rudolf Marek; Bao, Zheng; Coreboot
Subject: Re: [coreboot] 4 GB RAM failure on DBM690T target (690G/SB600)

On Tue, Jan 20, 2009 at 6:50 PM, Carl-Daniel Hailfinger
 wrote:
> On 20.01.2009 17:13, Rudolf Marek wrote:
> > > I'm not totally sure the ACPI code is hard coded to 1 GB. The

default
> > > values in the ACPI code code correspond to 1 GB and there is some

code
> > > which will calculate BIOS memory location from TOM and TOM2. I could

not
> > > find any place where TOM and TOM2 are updated,
> >
> > its in acpi-k8.c in amd directory. Its in ssdt table.
>
> Thanks. Unfortunately, the situation is more complicated on DBM690T.
> TOM (the top below 4 GB) is stored twice, once in the SSDT (modified
> automatically) and once in the DSDT (unmodified). TOM2 is only stored

in
> the DSDT (unmodified). The (correct) value of TOM in the SSDT is

ignored
> and the (incorrect) values of TOM/TOM2 in the DSDT are used.

This sounds like a oversite. Maybe the AMD BTDC guys can help.
Marc

[Carl-Daniel Hailfinger]

On 21.01.2009 09:04, Bao, Zheng wrote:
> We will try to debug this after the Chinese New Year.

Thank you!

My mainboard is now a few hundred km away and I will not have access to
it before end of January, so it is a low priority for me.
> Now I am debugging the shiner (RS780/SB700). The board will be returned
> in a week, so I have to focus on this. Now most of the feature is
> working, except VGA.

Wow, that is really great. Thank you for working on this new platform
and good luck!

Regards,
Carl-Daniel