If anyone needs code for either of these two SuperIOs, let me know, I've ported the lpc47b397 code and it should work fine, but I don't want to go submitting it until it's tested, and the only boards I have with these chips are 440bx based. BTW, have there been any requests for Slot A Athlon support, namely the AMD 751 northbridge and Via 686a southbridge chips? I'm seriously considering working on all 3 of these, just acquired a board (FIC SPII) and a couple extra BIOS chips that I'm sure can be forced to work, although the DOS flasher doesn't like them.
On Sun, Nov 12, 2006 at 12:34:29AM -0500, Corey Osgood wrote:
If anyone needs code for either of these two SuperIOs, let me know, I've ported the lpc47b397 code and it should work fine, but I don't want to go submitting it until it's tested, and the only boards I have with these chips are 440bx based.
In case you're waiting for my 440BX code here - that's not needed. The Super I/O stuff will work fine even before RAM init. Just use the current bitworks/ims code and replace the Super I/O stuff there for testing the serial console...
BTW, have there been any requests for Slot A Athlon support, namely the AMD 751 northbridge and Via 686a southbridge chips? I'm seriously considering working on all 3 of these,
That would be great! We're happy about any patches you can provide :)
Uwe.
Uwe Hermann wrote:
In case you're waiting for my 440BX code here - that's not needed. The Super I/O stuff will work fine even before RAM init. Just use the current bitworks/ims code and replace the Super I/O stuff there for testing the serial console...
Err...the two boards I have with those superio's are the damn intels with the tsops, so they need somewhat of a guarantee of booting (and being able to be reflashed) before I can test them.
BTW, have there been any requests for Slot A Athlon support, namely the AMD 751 northbridge and Via 686a southbridge chips? I'm seriously considering working on all 3 of these,
That would be great! We're happy about any patches you can provide :)
Alright, I'm already working on it. This southbridge has an integrated Super I/O, should I be including the Super I/O code in with the southbridge, or seperating them out? Or does it really matter? Seem to me that the first way would be easier, but the second would make it easier to debug, and in case there are other motherboards that use the same southbridge but an off-chip super io (dunno if there are any). I haven't looked yet to see how v1 does it. Anyways, let me know, I can do it either way (currently still working on making sure the CPU works right, these early athlons were a bit funky, from what I've read so far).
-Corey
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Corey Osgood -
Uwe Hermann