Hi,
here's the output I get when running LinuxBIOS ony my GA-6BXC board, using the fixed IT8671F code from svn, and an almost unmodified bitworks/ims code.
I have 3 RAM slots (all used); does the output look good? Where should I continue now? One thing I'll have to figure out is to build a payload which prints some stuff to the serial port, so I know that the payload is reached.
The monitor stays black, which code do I need to touch to get VGA output?
Cheers, Uwe.
I have 3 RAM slots (all used); does the output look good?
Yes thats looks ok.
Where should I continue now? One thing I'll have to figure out is to build a payload which prints some stuff to the serial port, so I know that the payload is reached.
Um.... You need to go re-read all the thread postings on the i44bx and V2. Its not even close to running a payload.
Thats it. Thats all the code base does right now is dump out the RAM spd. Thats the tip of the iceberg.
Next we have to actually make the RAM work. Then we load and jump to linux bios. Then we discover and config all the necessary devices on the pci bus Then we can try to load a payload.
The next step is to copy the RAM init code from the Intel e7501 nortbridge (raminit.c) over whats in the i440bx directory. Then start comparing that code to what V1 does in 440bx/raminit.inc and fix it up so it works.
The e7501 is a DDR controller but a lot of the terminology is the same as the SDRAM controller in the 440bx and the structure of the file is sane and very well commented. It also has some stuff in there about ECC ram which we would eventually like to support.
Hi,
On Fri, Aug 11, 2006 at 01:32:45PM -0500, Richard Smith wrote:
Um.... You need to go re-read all the thread postings on the i44bx and V2. Its not even close to running a payload.
Thats it. Thats all the code base does right now is dump out the RAM spd. Thats the tip of the iceberg.
Next we have to actually make the RAM work. Then we load and jump to linux bios. Then we discover and config all the necessary devices on the pci bus Then we can try to load a payload.
The next step is to copy the RAM init code from the Intel e7501 nortbridge (raminit.c) over whats in the i440bx directory. Then start comparing that code to what V1 does in 440bx/raminit.inc and fix it up so it works.
The e7501 is a DDR controller but a lot of the terminology is the same as the SDRAM controller in the 440bx and the structure of the file is sane and very well commented. It also has some stuff in there about ECC ram which we would eventually like to support.
OK, sounds like a lot of work... As I'm not an expert with all this low-level stuff it'll take a while until I read and understand all the code and datasheets...
In the mean time, here's a patch which forks the bitworks/ims code and adds a gigabyte/ga-6bxc target with some minor changes...
Cheers, Uwe.
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Richard Smith -
Uwe Hermann