New patch to review for coreboot: bf9d8a4 Intel 82801dx: compile early_smbus as separate object
Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/909
-gerrit
commit bf9d8a4a9e91db3483353d568cf176d817b283e5 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Fri Apr 20 17:11:31 2012 +0300
Intel 82801dx: compile early_smbus as separate object
Add early_smbus.c for romstage-y list and remove respective include on mainboard romstage.c files.
Tested on AOpen board.
Change-Id: I1c7e6cb32e3a9d7cc9b6037dc27e59149d492001 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/aopen/dxplplusu/romstage.c | 2 - src/mainboard/digitallogic/adl855pc/romstage.c | 1 - src/mainboard/lanner/em8510/romstage.c | 1 - src/mainboard/rca/rm4100/romstage.c | 1 - src/mainboard/thomson/ip1000/romstage.c | 1 - src/southbridge/intel/i82801dx/Makefile.inc | 2 + src/southbridge/intel/i82801dx/early_smbus.c | 26 ++++++----------------- src/southbridge/intel/i82801dx/i82801dx.h | 5 ++++ 8 files changed, 14 insertions(+), 25 deletions(-)
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 73e445b..188d404 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -31,8 +31,6 @@ #include <spd.h>
#include "southbridge/intel/i82801dx/i82801dx.h" -#include "southbridge/intel/i82801dx/early_smbus.c" -#include "southbridge/intel/i82801dx/reset.c" #include "northbridge/intel/e7505/raminit.h" #include "northbridge/intel/e7505/debug.c" #include "superio/smsc/lpc47m10x/early_serial.c" diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 16b15fe..d1a7622 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -10,7 +10,6 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include "southbridge/intel/i82801dx/i82801dx.h" -#include "southbridge/intel/i82801dx/early_smbus.c" #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" #include "superio/winbond/w83627hf/early_serial.c" diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 874e730..dbe769e 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -33,7 +33,6 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include "southbridge/intel/i82801dx/i82801dx.h" -#include "southbridge/intel/i82801dx/early_smbus.c" #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" #include "superio/winbond/w83627thg/early_serial.c" diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 415e2ac..692e5b0 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -36,7 +36,6 @@ #include "cpu/x86/bist.h" #include "spd_table.h" #include "gpio.c" -#include "southbridge/intel/i82801dx/early_smbus.c" #include "southbridge/intel/i82801dx/tco_timer.c"
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index e85de94..7ce89ad 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -37,7 +37,6 @@ #include "cpu/x86/bist.h" #include "spd_table.h" #include "gpio.c" -#include "southbridge/intel/i82801dx/early_smbus.c" #include "southbridge/intel/i82801dx/tco_timer.c"
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 9070158..9644210 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -31,3 +31,5 @@ ramstage-y += reset.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 00eaee0..1387525 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -18,26 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include "i82801dx.h" +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <console/console.h>
-#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -//#define SMBUS_TIMEOUT (100*1000*10) +#include "i82801dx.h"
-static void enable_smbus(void) +void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
@@ -112,7 +100,7 @@ static int smbus_wait_until_done(void) return loops ? 0 : -3; }
-static int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned device, unsigned address) { unsigned char global_status_register; unsigned char byte; diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index a38c793..4da430a 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -31,9 +31,14 @@ #ifndef I82801DX_H #define I82801DX_H
+#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801dx_enable(device_t dev); +#else +void enable_smbus(void); +int smbus_read_byte(unsigned device, unsigned address); +#endif #endif
/*
-
Kyösti Mälkki