Board is built in Igel Thin Client 3210
After a few problems, http://www.coreboot.org/pipermail/coreboot/2012-March/068553.html
now the board starts with coreboot, but very often coreboot hangs. It is very crazy. Sometimes the board starts three or fourtimes without problems, and sometimes I have to push very often the power button to get it start.
There are many selfmade debug lines in the code at the moment and it seems to work better, now.
Mainboard tree is BCOM/winnetp680
in romstage.c The main loop calls ddr_ram_setup() in src/northbridge/via/cn700/raminit.c This function calls c7_cpu_setup() in the same file first. Normaly a few registers should set now with pci_write_config8() but nothing happens.
If coreboot hangs the first pci_write_config8() function isn`t done.
static void c7_cpu_setup(device_t dev) { --> A debug line here says the function is entered
/* Host bus interface registers (D0F2 0x50-0x67) */ /* Request phase control */ pci_write_config8(dev, 0x50, 0x88); <-- Debug in pci_ops.c says nothing happens /* CPU Interface Control */ pci_write_config8(dev, 0x51, 0x7a); pci_write_config8(dev, 0x52, 0x6f); /* Arbitration */ pci_write_config8(dev, 0x53, 0x88);
Can anybody help. I can`t find the CN700 Datasheet is the CX700 close to CN700. What could be the reason for this problem. Timing issues? pci_ops.c get_pbus don`t find the cpu on the bus?
With the many debug coreboot is slower than factory bios. With Console Debug set to 0 the board don't starts.
Mainboard Winnet G270 Ver. 0.3 C7 Via Esther CPU 600MHz CN700 Northbridge VT8237R+ Southbridge W83697HF SuperIO
1x DVI 1x VGA 1x COM (Second Pinheader for COM2 not soldered) 1x LPT 1x 100/10 RJ54 Network 2x Audio (Mic/Line)
1x CF-Card Slot IDE1 on board 1x 44 Pin Header for 2,5" HDD IDE1 256MB SO-DIMM DDR2 533MHz
chris
static void c7_cpu_setup(device_t dev) { --> A debug line here says the function is entered
/* Host bus interface registers (D0F2 0x50-0x67) */ /* Request phase control */ pci_write_config8(dev, 0x50, 0x88); <-- Debug in pci_ops.c says nothing happens
Oh sorry, pci_ops.c wasn`t the right place.
Coreboot hangs after writing offset 56 in c7_cpu_setup I have changed the function like the raminit.c from cn400.
First write offset 70-83 write offset 50 write offset 60-67 write offset 51,52,53 write offset 59-5f write offset 55,56 finally write offset 54
and it seems to work now.
Now there are a question for me. Can I easily insert a new line for my 600MHz CPU in cpu/via/c7/c7_init.c --> static int xxx_speed_translation.
chris
Now there are a question for me. Can I easily insert a new line for my 600MHz CPU in cpu/via/c7/c7_init.c --> static int xxx_speed_translation.
oh no, what a mess. It is a VIA Eden CPU. I`m not sure if it very different to C7 Somewhere I have read a Igel 3210 has a C7 CPU and known that.
Currently all works fine but coreboot decided to set the CPU to 4x100MHz.
Who can help to change the speed_translation function.
chris
Who can help to change the speed_translation function.
Here is the log ...
Initializing CPU #0 CPU: vendor Centaur device 6a9 CPU: family 06, model 0a, stepping 09 Detected VIA Model A Eden Enabling improved C7 clock and voltage. Voltage: 844mV (min 844mV; max 844mV) --> That is all correct CPU multiplier: 4x (min 4x; max 6x) --> multiplier should be 6 msr.lo = 4000409
--> here the function compares the values there is no VIA Eden 600MHz CPU in c7a_speed_translation so
new msr.lo = 409
Current voltage: 844mV <-- right Current CPU multiplier: 4x <-- wrong, should be 6
For Via Model A Eden I have to change the
static int c7a_speed_translation[] = { // LFM HFM 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V 0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V 0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV 0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV };
LFM is 0x0409 but I`m unsure for HFM and should I change the c7d_speed_translation, too?
chris
For Via Model A Eden I have to change the
static int c7a_speed_translation[] = { // LFM HFM
0x0409, 0x0609 // 400MHz, 844mV --> 600MHz, 844mV Eden insert this line for Via Eden 600MHz CPU
0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V 0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V 0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV 0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV };
I`m not sure about DRAM Frequency Loading the kernel is a little bit slower as with factoy Bios, should be 266MHZ.
chris
-
Christian