Hello,
Does coreboot support executing of boostrap which is contained in MBR? Maybe you have any hints about writing payload which can do that?
Thanks in advance,
On Tue, 23 Feb 2010 13:58:30 +0100, Piotr Piwko piotr.piwko@embedded-engineering.pl wrote:
Hello,
Does coreboot support executing of boostrap which is contained in MBR? Maybe you have any hints about writing payload which can do that?
SeaBIOS
Piotr Piwko wrote:
Does coreboot support executing of boostrap which is contained in MBR?
No. coreboot itself doesn't really do operating system bootstrapping.
Maybe you have any hints about writing payload which can do that?
As Joseph pointed out you could look at SeaBIOS, which has quickly become a very complete BIOS implementation. SeaBIOS runs well as a coreboot payload, and if you combine coreboot and SeaBIOS you will indeed have a legacy compatible open source firmware.
//Peter
2010/2/23 Peter Stuge peter@stuge.se:
As Joseph pointed out you could look at SeaBIOS, which has quickly become a very complete BIOS implementation. SeaBIOS runs well as a coreboot payload, and if you combine coreboot and SeaBIOS you will indeed have a legacy compatible open source firmware.
I'm afraid that I will have to write my own part of code which will be responsible to execute a boostrap. At this moment I use the old version of coreboot project (practically LinuxBIOS 2.0.0), because only in this release my target board (MSM800BEV) is fully supported out of the box. Unfortunately, it doesn't contain the
uint64_t high_tables_base = 0; uint64_t high_tables_size;
variables which are necessary to proper SeaBIOS work (according with http://www.coreboot.org/SeaBIOS document).
Maybe do you have any documents or advices about using SeaBIOS with this coreboot version?
Thanks for your interest.
On 24.02.2010 08:38, Piotr Piwko wrote:
2010/2/23 Peter Stuge peter@stuge.se:
As Joseph pointed out you could look at SeaBIOS, which has quickly become a very complete BIOS implementation. SeaBIOS runs well as a coreboot payload, and if you combine coreboot and SeaBIOS you will indeed have a legacy compatible open source firmware.
I'm afraid that I will have to write my own part of code which will be responsible to execute a boostrap.
That means you have to recreate maybe 90% of SeaBIOS. You need harddisk drivers, interrupt services, ... Changing SeaBIOS to work in your environment will be way easier. The SeaBIOS mailing list http://seabios.org/Mailinglist is the preferred way to ask for help with that.
Regards, Carl-Daniel
Piotr Piwko wrote:
I'm afraid that I will have to write my own part of code which will be responsible to execute a boostrap. At this moment I use the old version of coreboot project (practically LinuxBIOS 2.0.0), because only in this release my target board (MSM800BEV) is fully supported out of the box.
It would really be nice if you could help make this target work with the updated coreboot sources.
I would actually expect this to require only moderate effort.
Unfortunately, it doesn't contain the
uint64_t high_tables_base = 0; uint64_t high_tables_size;
variables which are necessary to proper SeaBIOS work (according with http://www.coreboot.org/SeaBIOS document).
Maybe do you have any documents or advices about using SeaBIOS with this coreboot version?
Then there are basically two choices;
1. Backport support for high tables from current code 2. Fix current code for your target
I would strongly prefer option 2.
Can you show us boot logs from your working version and from the very latest version?
//Peter
2010/2/24 Peter Stuge peter@stuge.se:
Piotr Piwko wrote:
I'm afraid that I will have to write my own part of code which will be responsible to execute a boostrap. At this moment I use the old version of coreboot project (practically LinuxBIOS 2.0.0), because only in this release my target board (MSM800BEV) is fully supported out of the box.
It would really be nice if you could help make this target work with the updated coreboot sources.
I would really like to do this job, but unfortunately I currently work on the quite urgent project and I don't enough time and energy to join to another project. Anyway, I am impressed with your work and I hope that I will be able to help in the future.
Then there are basically two choices;
- Backport support for high tables from current code
- Fix current code for your target
I would strongly prefer option 2.
I've decided to write my own code to execute bootstrap from MBR. At this moment I test the functions which are responsible for ATA protocol support. If I have any positive results, I will post my observations.
Can you show us boot logs from your working version and from the very latest version?
I'm going to do this as soon as possible.
-----Original Message----- From: coreboot-bounces+mylesgw=gmail.com@coreboot.org [mailto:coreboot- bounces+mylesgw=gmail.com@coreboot.org] On Behalf Of Piotr Piwko Sent: Wednesday, February 24, 2010 11:59 AM To: coreboot@coreboot.org Subject: Re: [coreboot] Executing bootstrap from MBR in coreboot
2010/2/24 Peter Stuge peter@stuge.se:
Piotr Piwko wrote:
I'm afraid that I will have to write my own part of code which will be responsible to execute a boostrap. At this moment I use the old version of coreboot project (practically LinuxBIOS 2.0.0), because only in this release my target board (MSM800BEV) is fully supported out of the box.
It would really be nice if you could help make this target work with the updated coreboot sources.
I would really like to do this job, but unfortunately I currently work on the quite urgent project and I don't enough time and energy to join to another project. Anyway, I am impressed with your work and I hope that I will be able to help in the future.
Given the boot logs it's very possible that someone on the list will fix it for you. In most cases it only takes a few iterations.
Thanks, Myles
2010/2/24 Myles Watson mylesgw@gmail.com:
Given the boot logs it's very possible that someone on the list will fix it for you. In most cases it only takes a few iterations.
We were discussing about fixing this coreboot-v3 bug in my previous thread (http://www.mail-archive.com/coreboot@coreboot.org/msg21110.html) and I didn't get any positive results. I think that the memory controller initialization process is not carried out in the proper way. I've even talked with AMD guys who gave me some hints, but unfortunately it must be postponed for a while and wait for my free time.
They have some objections about the following registers: - MC_CF1017_DATA (0x2000001a) should be equal something more like 0x00000000_140DD101 instead of 0x00000000_00000101 - GLCP_DELAY_CONTROLS (0x4c00000f) should be closer to something like 0xF2F100FF_56960004
Below, there is complete list of registers which are related with memory controller. Of course, I get it after coreboot-v3 memory initialization process:
CPU_PF_CONF (0x00001100): 0x00000100_00005051 GLIU0_ARB (0x10000082): 0x80000000_00000000 GLIU1_ARB (0x40000082): 0x80000000_00000000 GLIU1_PORT_ACTIVE (0x40000081): 0x00000000_0000c77f CPU_AC_SMM_CTL (0x00001301): 0x00000000_00000008 CPU_FPU_MSR_MODE (0x00001a00): 0x00000000_00000001 CPU_XC_CONFIG (0x00001210): 0x00000000_00000003 CPU_BC_CONF_0 (0x00001900): 0x00000000_02001131 GLCP_DBGCLKCTL (0x4c000016): 0x00000000_00000002 GLCP_TH_OD (0x4c00001e): 0x00000000_0000603c MC_CF1017_DATA (0x2000001a): 0x00000000_00000101 MC_CF07_DATA (0x20000018): 0x10075012_00003400 MC_CF8F_DATA (0x20000019): 0x18000100_287337a3 MC_CFCLK_DBUG (0x2000001d): 0x00000000_00001000 GLCP_DELAY_CONTROLS (0x4c00000f): 0x830d415a_8ea0a36a MC_CF_PMCTR (0x20000020): 0x00000000_00000006 MDD_SOFT_RESET (0x51400017): 0x00000000_00000000 MC_GLD_MSR_PM (0x20002004): 0x00000000_00000001 GLCP_SYS_RSTPLL (0x4c000014): 0x0000049c_07de000c
Anyway, as you've suggested, I'm sending my logs of successful LinuxBIOS and failure coreboot-v3 startup process. I hope they will help.
On Thu, Feb 25, 2010 at 7:58 AM, Piotr Piwko piotr.piwko@gmail.com wrote:
2010/2/24 Myles Watson mylesgw@gmail.com:
Given the boot logs it's very possible that someone on the list will fix
it
for you. In most cases it only takes a few iterations.
We were discussing about fixing this coreboot-v3 bug in my previous thread (http://www.mail-archive.com/coreboot@coreboot.org/msg21110.html)
Sorry about my misunderstanding. I should have looked to see that your board was a Geode-based board.
Anyway, as you've suggested, I'm sending my logs of successful LinuxBIOS and failure coreboot-v3 startup process.
I was actually hoping for the log from the failure of the current v2 head. Very few people are interested in fixing v3. Maybe one of them will take you up on it, though.
Thanks, Myles
On 25.02.2010 16:04, Myles Watson wrote:
On Thu, Feb 25, 2010 at 7:58 AM, Piotr Piwko piotr.piwko@gmail.com wrote:
2010/2/24 Myles Watson mylesgw@gmail.com:
Given the boot logs it's very possible that someone on the list will fix it for you. In most cases it only takes a few iterations.
The "someone on the list" would be me. I still care about v3 and Geode, but my feature/bugfix request backlog is huge, and I can't start before end of April at the earliest, so my best bet would be September before I can tackle this. And even then, I probably won't have time to focus on hardware I don't own.
We were discussing about fixing this coreboot-v3 bug in my previous thread (http://www.mail-archive.com/coreboot@coreboot.org/msg21110.html)
Sorry about my misunderstanding. I should have looked to see that your board was a Geode-based board.
Anyway, as you've suggested, I'm sending my logs of successful LinuxBIOS and failure coreboot-v3 startup process.
I was actually hoping for the log from the failure of the current v2 head. Very few people are interested in fixing v3. Maybe one of them will take you up on it, though.
Piotr, you said that the project is time critical. As I wrote above, my help would come too late for you. Maybe you can ask coresystems for an offer.
Regards, Carl-Daniel
2010/2/25 Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net:
The "someone on the list" would be me. I still care about v3 and Geode, but my feature/bugfix request backlog is huge, and I can't start before end of April at the earliest, so my best bet would be September before I can tackle this. And even then, I probably won't have time to focus on hardware I don't own.
I'm thankful for your engagement and I fully understand you. Now, it will be better if you focus on your final exams :) Good luck!
On Thu, Feb 25, 2010 at 7:58 AM, Piotr Piwko piotr.piwko@gmail.com wrote:
2010/2/24 Myles Watson mylesgw@gmail.com:
Given the boot logs it's very possible that someone on the list will fix it for you. In most cases it only takes a few iterations.
We were discussing about fixing this coreboot-v3 bug in my previous thread (http://www.mail-archive.com/coreboot@coreboot.org/msg21110.html) and I didn't get any positive results. I think that the memory controller initialization process is not carried out in the proper way. I've even talked with AMD guys who gave me some hints, but unfortunately it must be postponed for a while and wait for my free time.
They have some objections about the following registers:
- MC_CF1017_DATA (0x2000001a) should be equal something more like
0x00000000_140DD101 instead of 0x00000000_00000101
- GLCP_DELAY_CONTROLS (0x4c00000f) should be closer to something like
0xF2F100FF_56960004
I think you are correct. This looks like the memory init is not able to get correct information from the SPD. If that is the problem, you should check that the SMBus controller setup is correct.
Marc
2010/2/26 Marc Jones marcj303@gmail.com:
They have some objections about the following registers:
- MC_CF1017_DATA (0x2000001a) should be equal something more like
0x00000000_140DD101 instead of 0x00000000_00000101
- GLCP_DELAY_CONTROLS (0x4c00000f) should be closer to something like
0xF2F100FF_56960004
I think you are correct. This looks like the memory init is not able to get correct information from the SPD. If that is the problem, you should check that the SMBus controller setup is correct.
Ok, I'm going to check it.
Piotr Piwko wrote:
my target board (MSM800BEV)
It would really be nice if you could help make this target work with the updated coreboot sources.
I would really like to do this job, but unfortunately I currently work on the quite urgent project and I don't enough time and energy to join to another project.
I consider this to be the same project. You are using coreboot after all.
Anyway, I am impressed with your work and I hope that I will be able to help in the future.
You can help, right now. I am pretty sure it will be a lot less work than writing your own bootloader.
I've decided to write my own code to execute bootstrap from MBR. At this moment I test the functions which are responsible for ATA protocol support.
As I am sure you already know there are already several ATA drivers in the coreboot ecosystem. SeaBIOS even supports DMA, which has major impact on boot speed.
Can you show us boot logs from your working version and from the very latest version?
I'm going to do this as soon as possible.
That's good. It is absolutely neccessary for you to get any help at all. Of course there is no guarantee that anyone can help immediately.
//Peter
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Carl-Daniel Hailfinger -
Joseph Smith -
Marc Jones -
Myles Watson -
Peter Stuge -
Piotr Piwko -
Piotr Piwko