Hi all,
I'm going through coreboot sources _looking for a chipset with working SDRAM support_ and came across this:
/usr/src/coreboot/src/northbridge/amd/gx1/northbridge.h: #ifndef NORTHBRIDGE_INTEL_440BX_H #define NORTHBRIDGE_INTEL_440BX_H
extern unsigned int i440bx_scan_root_bus(device_t root, unsigned int max);
#endif /* NORTHBRIDGE_INTEL_440BX_H */
I grepped for more references to this and got:
buurin@htcore:/usr/src/coreboot$ grep "i440bx_scan_root_bus" -R * src/northbridge/amd/gx1/.svn/text-base/northbridge.h.svn-base:extern unsigned int i440bx_scan_root_bus(device_t root, unsigned int max); src/northbridge/amd/gx1/northbridge.h:extern unsigned int i440bx_scan_root_bus(device_t root, unsigned int max); src/northbridge/intel/i440bx/.svn/text-base/northbridge.h.svn-base:extern unsigned int i440bx_scan_root_bus(device_t root, unsigned int max); src/northbridge/intel/i440bx/northbridge.h:extern unsigned int i440bx_scan_root_bus(device_t root, unsigned int max); buurin@htcore:/usr/src/coreboot$
Does it serve a purpose at all in the AMD GX1 sub-tree?
Yes, I am working on 440BX SDRAM support and still looking for a board with working SDRAM support in coreboot so I can borrow some ideas. The closest I find is i810 in MS6178 and that's also a WIP. I'll look some more but for now I know just programming the DRAM row boundary is not enough. Coreboot fails at decompressing its payload. BTW I have a dead MS6178 that I salvaged quite a few parts from. :-D
Thanks Keith
Yes, I am working on 440BX SDRAM support and still looking for a board
with
working SDRAM support in coreboot so I can borrow some ideas. The closest
I
find is i810 in MS6178 and that's also a WIP. I'll look some more but for now I know just programming the DRAM row boundary is not enough. Coreboot fails at decompressing its payload. BTW I have a dead MS6178 that I salvaged quite a few parts from. :-D
FYI, take a look at the i830 raminit. It works really slick.
-
Joseph Smith -
Keith Hui