r3761 - in trunk/coreboot-v2: src/mainboard/lippert/roadrunner-lx targets/lippert/roadrunner-lx

Author: uwe
Date: 2008-11-19 14:42:14 +0100 (Wed, 19 Nov 2008)
New Revision: 3761

Modified:
   trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb
   trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb
   trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h
   trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c
   trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c
   trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb
Log:
Coding-style and whitespace fixes (also to make the code more similar
the Lippert Cool SpaceRunner LX which is already in svn).

Signed-off-by: Uwe Hermann 
Acked-by: Uwe Hermann

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb	2008-11-19 12:19:09 UTC (rev 3760)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb	2008-11-19 13:42:14 UTC (rev 3761)
@@ -3,8 +3,6 @@
 ##
 ## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
 ##
-## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
@@ -20,15 +18,17 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##

+## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
+
 ##
 ## Compute the location and size of where this firmware image
 ## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
    default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
 else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_SIZE   = (ROM_SIZE - FALLBACK_SIZE)
    default ROM_SECTION_OFFSET = 0
 end

@@ -38,12 +38,12 @@
 ##

default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE			= ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default PAYLOAD_SIZE             = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)

##
 ## Compute where this copy of coreboot will start in the boot rom
 ##
-default _ROMBASE	  = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)

##
 ## Compute a range of ROM that can cached to speed up coreboot,
@@ -52,8 +52,8 @@
 ## XIP_ROM_SIZE must be a power of 2.
 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
 ##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+default XIP_ROM_SIZE = 64 * 1024
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)

##
@@ -73,12 +73,12 @@
 end

if USE_DCACHE_RAM
-	#compile cache_as_ram.c to auto.inc
+	# compile cache_as_ram.c to auto.inc
    makerule ./cache_as_ram_auto.inc
-			depends "$(MAINBOARD)/cache_as_ram_auto.c"
-			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
-			action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+		depends "$(MAINBOARD)/cache_as_ram_auto.c"
+		action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+		action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
    end
 end

@@ -136,97 +136,100 @@
 end

##
-## Include the secondary Configuration files
+## Include the secondary configuration files
 ##
 dir /pc80
 config chip.h
-register "sio_gp1x_config" = "0x20" # bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED

+# Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED.
+register "sio_gp1x_config" = "0x20"
+
 chip northbridge/amd/lx
-	device pci_domain 0 on
-		device pci 1.0 on end				# Northbridge
-		device pci 1.1 on end				# Graphics
-		device pci 1.2 on end				# AES
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
-			register "lpc_serirq_enable"   = "0x000012DA"	# 00010010 11011010
-			register "lpc_serirq_polarity" = "0x0000ED25"	# inverse of above
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0"	# 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	# 0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x3E8"
-			register "com1_irq" = "6"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2E8"
-			register "com2_irq" = "6"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci 8.0 on end			# Slot4
-			device pci 9.0 on end			# Slot3
-			device pci a.0 on end			# Slot2
-			device pci b.0 on end			# Slot1
-			device pci c.0 on end			# IT8888
-			device pci e.0 on end			# Ethernet
-			device pci f.0 on			# ISA Bridge
-				chip superio/ite/it8712f
-					device pnp 2e.0 off #  Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.1 on #  Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.2 on #  Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.3 on #  Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.4 on #  EC
-						io 0x60 = 0x290
-						io 0x62 = 0x230
-						irq 0x70 = 9
-					end
-					device pnp 2e.5 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-					end
-					device pnp 2e.6 on #  Mouse
-						irq 0x70 = 12
-					end
-					device pnp 2e.7 on #  GPIO
-						io 0x62 = 0x1220
-						#io 0x64 = 0x1200
-					end
-					device pnp 2e.8 off #  MIDI
-						io 0x60 = 0x300
-						irq 0x70 = 9
-					end
-					device pnp 2e.9 off #  GAME
-						io 0x60 = 0x220
-					end
-					device pnp 2e.a off end #  CIR
-				end
-			end
-			device pci f.2 on end			# IDE Controller
-			device pci f.3 on end			# Audio
-			device pci f.4 on end			# OHCI
-			device pci f.5 on end			# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
+  device pci_domain 0 on
+    device pci 1.0 on end		# Northbridge
+    device pci 1.1 on end		# Graphics
+    device pci 1.2 on end		# AES
+    chip southbridge/amd/cs5536		# Southbridge
+      # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
+      # SIRQ Mode = Active(Quiet) mode. Save power...
+      # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
+      # UARTs, etc IRQs. OK
+      register "lpc_serirq_enable"        = "0x000012DA"  # 00010010 11011010
+      register "lpc_serirq_polarity"      = "0x0000ED25"  # inverse of above
+      register "lpc_serirq_mode"          = "1"
+      register "enable_gpio_int_route"    = "0x0D0C0700"
+      register "enable_ide_nand_flash"    = "0"  # 0:ide mode, 1:flash
+      register "enable_USBP4_device"      = "0"  # 0: host, 1:device
+      register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+      register "com1_enable"              = "0"
+      register "com1_address"             = "0x3E8"
+      register "com1_irq"                 = "6"
+      register "com2_enable"              = "0"
+      register "com2_address"             = "0x2E8"
+      register "com2_irq"                 = "6"
+      register "unwanted_vpci[0]"         = "0"  # End of list has a zero
+      device pci 8.0 on end		# Slot4
+      device pci 9.0 on end		# Slot3
+      device pci a.0 on end		# Slot2
+      device pci b.0 on end		# Slot1
+      device pci c.0 on end		# IT8888
+      device pci e.0 on end		# Ethernet
+      device pci f.0 on			# ISA bridge
+        chip superio/ite/it8712f
+          device pnp 2e.0 off		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on		# Com1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.2 on		# Com2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.4 on		# EC
+            io 0x60 = 0x290
+            io 0x62 = 0x230
+            irq 0x70 = 9
+          end
+          device pnp 2e.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.6 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.7 on		# GPIO
+            io 0x62 = 0x1220
+            # io 0x64 = 0x1200
+          end
+          device pnp 2e.8 off		# MIDI
+            io 0x60 = 0x300
+            irq 0x70 = 9
+          end
+          device pnp 2e.9 off		# Game port
+            io 0x60 = 0x220
+          end
+          device pnp 2e.a off end	# CIR
+        end
+      end
+      device pci f.2 on end		# IDE controller
+      device pci f.3 on end		# Audio
+      device pci f.4 on end		# OHCI
+      device pci f.5 on end		# EHCI
+    end
+  end
+  # APIC cluster is late CPU init.
+  device apic_cluster 0 on
+    chip cpu/amd/model_lx
+      device apic 0 on end
+    end
+  end
 end

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb	2008-11-19 12:19:09 UTC (rev 3760)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb	2008-11-19 13:42:14 UTC (rev 3761)
@@ -3,8 +3,6 @@
 ##
 ## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
 ##
-## Based on Options.lb from AMD's DB800 mainboard.
-##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
@@ -20,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##

+## Based on Options.lb from AMD's DB800 mainboard.
+
 uses HAVE_MP_TABLE
 uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
@@ -80,71 +80,71 @@
 uses PIRQ_ROUTE

## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE  = 512*1024
+default ROM_SIZE = 512 * 1024

###
 ### Build options
 ###
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_VIDEO_MB=8
-default CONFIG_PCI_ROM_RUN=0
+default CONFIG_CONSOLE_VGA = 0
+default CONFIG_VIDEO_MB = 8
+default CONFIG_PCI_ROM_RUN = 0

##
 ## Build code for the fallback boot
 ##
-default HAVE_FALLBACK_BOOT=1
+default HAVE_FALLBACK_BOOT = 1

##
 ## no MP table
 ##
-default HAVE_MP_TABLE=0
+default HAVE_MP_TABLE = 0

##
 ## Build code to reset the motherboard from coreboot
 ##
-default HAVE_HARD_RESET=0
+default HAVE_HARD_RESET = 0

## Delay timer options
 ##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1

##
 ## Build code to export a programmable irq routing table
 ##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=7
-default PIRQ_ROUTE=1
+default HAVE_PIRQ_TABLE = 1
+default IRQ_SLOT_COUNT = 7
+default PIRQ_ROUTE = 1

##
 ## Build code to export a CMOS option table
 ##
-default HAVE_OPTION_TABLE=0
+default HAVE_OPTION_TABLE = 0

###
 ### coreboot layout values
 ###

## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+default ROM_IMAGE_SIZE = 64 * 1024
+default FALLBACK_SIZE = 128 * 1024

##
 ## enable CACHE_AS_RAM specifics
 ##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
+default USE_DCACHE_RAM = 1
+default DCACHE_RAM_BASE = 0xc8000
+default DCACHE_RAM_SIZE = 0x08000

##
 ## Use a small 8K stack
 ##
-default STACK_SIZE=0x2000
+default STACK_SIZE = 8 * 1024

##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default HEAP_SIZE = 16 * 1024

##
 ## Only use the option table in a normal image
@@ -159,36 +159,36 @@
 ##
 ## The default compiler
 ##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CROSS_COMPILE = ""
+default CC = "$(CROSS_COMPILE)gcc -m32"
+default HOSTCC = "gcc"

##
 ## The Serial Console
 ##

# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
+default CONFIG_CONSOLE_SERIAL8250 = 1

## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default TTYS0_BAUD = 115200
+#default TTYS0_BAUD = 57600
+#default TTYS0_BAUD = 38400
+#default TTYS0_BAUD = 19200
+#default TTYS0_BAUD = 9600
+#default TTYS0_BAUD = 4800
+#default TTYS0_BAUD = 2400
+#default TTYS0_BAUD = 1200

# Select the serial console base port
-default TTYS0_BASE=0x3f8
+default TTYS0_BASE = 0x3f8

# Select the serial protocol
 # This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default TTYS0_LCS = 0x3

# Compile extra debugging code
-default DEBUG=1
+default DEBUG = 1

##
 ### Select the coreboot loglevel
@@ -204,8 +204,8 @@
 ## SPEW       9   Way too many details

## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  DEFAULT_CONSOLE_LOGLEVEL = 8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  MAXIMUM_CONSOLE_LOGLEVEL = 8

end

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c	2008-11-19 12:19:09 UTC (rev 3760)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c	2008-11-19 13:42:14 UTC (rev 3761)
@@ -4,8 +4,6 @@
  * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
  *
- * Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -21,6 +19,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+/* Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. */
+
 #define ASSEMBLY 1

#include <stdlib.h>
@@ -52,7 +52,9 @@

static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
-	if (device != DIMM0) return 0xFF;	// no DIMM1, don't even try
+	if (device != DIMM0)
+		return 0xFF;	/* No DIMM1, don't even try. */
+
    return smbus_read_byte(device, address);
 }

@@ -120,11 +122,12 @@
 {
    int i;

-	/* Init SuperIO WDT, GPIOs. Done early, WDT init may trigger reset! */
+	/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
    it8712f_enter_conf();
-	for (i=0; i<ARRAY_SIZE(sio_init_table); i++) {
+	for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
    	u16 val = sio_init_table[i];
-		outb((u8)val, SIO_INDEX); outb(val>>8, SIO_DATA);
+		outb((u8)val, SIO_INDEX);
+		outb(val >> 8, SIO_DATA);
    }
    it8712f_exit_conf();
 }
@@ -142,10 +145,11 @@

cs5536_early_setup();

-	/* Note: must do this AFTER the early_setup! It is counting on some
+	/*
+	 * Note: must do this AFTER the early_setup! It is counting on some
     * early MSR setup for CS5536.
     */
-	it8712f_enable_serial(0, TTYS0_BASE); // does not use its 1st parameter
+	it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter
    mb_gpio_init();
    uart_init();
    console_init();

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h	2008-11-19 12:19:09 UTC (rev 3760)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h	2008-11-19 13:42:14 UTC (rev 3761)
@@ -3,8 +3,6 @@
  *
  * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
  *
- * Based on chip.h from AMD's DB800 mainboard.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -20,10 +18,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+/* Based on chip.h from AMD's DB800 mainboard. */
+
 #include <stdint.h>

extern struct chip_operations mainboard_lippert_roadrunner_lx_ops;

struct mainboard_lippert_roadrunner_lx_config {
-	u8 sio_gp1x_config;	// bit5=Live LED, bit2=RS485_EN2, bit1=RS485_EN1
+	/* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */
+	u8 sio_gp1x_config;
 };

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c	2008-11-19 12:19:09 UTC (rev 3760)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c	2008-11-19 13:42:14 UTC (rev 3761)
@@ -3,8 +3,6 @@
  *
  * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
  *
- * Based on irq_tables.c from AMD's DB800 mainboard.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -20,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+/* Based on irq_tables.c from AMD's DB800 mainboard. */
+
 #include <arch/pirq_routing.h>
 #include <console/console.h>
 #include <arch/io.h>
@@ -47,7 +47,7 @@
 const struct irq_routing_table intel_irq_routing_table = {
    PIRQ_SIGNATURE,		/* u32 signature */
    PIRQ_VERSION,		/* u16 version   */
-	32 + 16 * IRQ_SLOT_COUNT,	/* there can be total 7 devices on the bus */
+	32 + 16 * IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */
    0x00,			/* Where the interrupt router lies (bus) */
    (0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
    0x00,			/* IRQs devoted exclusively to PCI usage */
@@ -55,17 +55,17 @@
    0x002B,			/* Device */
    0,			/* Crap (miniport) */
    {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
-	0xE0,			/*      u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	0xE0,			/* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
    {
-	 /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
-	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00},       {0x00, 0x00},       {0x00, 0x00}},       0x0, 0x0},	/* cpu */
-	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
-	 {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00},       {0x00, 0x00},       {0x00, 0x00}},       0x0, 0x0},	/* ethernet */
-	 {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},	/* slot1 */
-	 {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0},	/* slot2 */
-	 {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0},	/* slot3 */
-	 {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0},	/* slot4 */
+		/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+		/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
+		{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00},       {0x00, 0x00},       {0x00, 0x00}},       0x0, 0x0},	/* CPU */
+		{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
+		{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00},       {0x00, 0x00},       {0x00, 0x00}},       0x0, 0x0},	/* ethernet */
+		{0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},	/* slot1 */
+		{0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0},	/* slot2 */
+		{0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0},	/* slot3 */
+		{0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0},	/* slot4 */
    }
 };

Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c	2008-11-19 12:19:09 UTC (rev 3760)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c	2008-11-19 13:42:14 UTC (rev 3761)
@@ -3,8 +3,6 @@
  *
  * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
  *
- * Based on mainboard.c from AMD's DB800 mainboard.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -20,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+/* Based on mainboard.c from AMD's DB800 mainboard. */
+
 #include <stdlib.h>
 #include <stdint.h>
 #include <console/console.h>
@@ -29,13 +29,13 @@
 #include <device/pci_ids.h>
 #include "chip.h"

-static const u16 ec_init_table[] = {	// hi=data, lo=index
-	0x1900,		// enable monitoring
-	0x0351,		// TMPIN1,2 diode mode, TMPIN3 off
-	0x805C,		// unlock zero adjust
-	0x7056, 0x3C57,	// zero adjust TMPIN1,2
-	0x005C,		// lock zero adjust
-	0xD014		// also set FAN_CTL polarity to Active High
+static const u16 ec_init_table[] = {	/* hi=data, lo=index */
+	0x1900,		/* Enable monitoring */
+	0x0351,		/* TMPIN1,2 diode mode, TMPIN3 off */
+	0x805C,		/* Unlock zero adjust */
+	0x7056, 0x3C57,	/* Zero adjust TMPIN1,2 */
+	0x005C,		/* Lock zero adjust */
+	0xD014		/* Also set FAN_CTL polarity to Active High */
 };

static void init(struct device *dev)
@@ -44,22 +44,24 @@
    unsigned int gpio_base, i;
    printk_debug("LiPPERT RoadRunner-LX ENTER %s\n", __FUNCTION__);

-	/* Init CS5536 GPIOs */
-	gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0),
-				      PCI_BASE_ADDRESS_1) - 1;
-	outl(0x00000040, gpio_base + 0x00);	// GPIO6  value      1 - LAN_PD#
-	outl(0x00000040, gpio_base + 0x04);	// GPIO6  output     1 - LAN_PD#
-	outl(0x00000400, gpio_base + 0x34);	// GPIO10 in aux1    1 - THRM_ALRM#
-	outl(0x00000400, gpio_base + 0x20);	// GPIO10 input      1 - THRM_ALRM#
-	outl(0x08000000, gpio_base + 0x98);	// GPIO27 pull up    0 - PM-LED
+	/* Init CS5536 GPIOs. */
+	gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD,
+		    PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;

-	/* Init Environment Controller */
-	for (i=0; i<ARRAY_SIZE(ec_init_table); i++) {
+	outl(0x00000040, gpio_base + 0x00); // GPIO6  value      1 - LAN_PD#
+	outl(0x00000040, gpio_base + 0x04); // GPIO6  output     1 - LAN_PD#
+	outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1    1 - THRM_ALRM#
+	outl(0x00000400, gpio_base + 0x20); // GPIO10 input      1 - THRM_ALRM#
+	outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up    0 - PM-LED
+
+	/* Init Environment Controller. */
+	for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) {
    	u16 val = ec_init_table[i];
-		outb((u8)val, 0x0295); outb(val>>8, 0x0296);
+		outb((u8)val, 0x0295);
+		outb(val >> 8, 0x0296);
    }

-	outb(mb->sio_gp1x_config, 0x1220); // Simple-I/O GP17-10
+	outb(mb->sio_gp1x_config, 0x1220); /* Simple-I/O GP17-10 */
    printk_debug("LiPPERT RoadRunner-LX EXIT %s\n", __FUNCTION__);
 }

Modified: trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb	2008-11-19 12:19:09 UTC (rev 3760)
+++ trunk/coreboot-v2/targets/lippert/roadrunner-lx/Config.lb	2008-11-19 13:42:14 UTC (rev 3761)
@@ -25,24 +25,24 @@
 mainboard lippert/roadrunner-lx

# HACK to get the right TSC support.
-option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1

-option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
+option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
+option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0

## Load payload (e.g. Linux) from IDE.
-#option CONFIG_ROM_PAYLOAD=0
-#option CONFIG_IDE=1
-#option CONFIG_FS_PAYLOAD=1
-#option CONFIG_FS_EXT2=1
-#option AUTOBOOT_DELAY=0
-#option AUTOBOOT_CMDLINE="hda1:/payload.elf"
+#option CONFIG_ROM_PAYLOAD = 0
+#option CONFIG_IDE = 1
+#option CONFIG_FS_PAYLOAD = 1
+#option CONFIG_FS_EXT2 = 1
+#option AUTOBOOT_DELAY = 0
+#option AUTOBOOT_CMDLINE = "hda1:/payload.elf"

# Leave 36k for VSA. Usually board is equipped with a 512 KB FWH (LPC) flash,
 # however it can be replaced with a 1 MB chip.
-option ROM_SIZE=512*1024-36*1024
-#option ROM_SIZE=1024*1024-36*1024
-option FALLBACK_SIZE=ROM_SIZE
+option ROM_SIZE = (512 * 1024) - (36 * 1024)
+#option ROM_SIZE = (1024 * 1024) - (36 * 1024)
+option FALLBACK_SIZE = ROM_SIZE

#option DEFAULT_CONSOLE_LOGLEVEL = 4
 #option MAXIMUM_CONSOLE_LOGLEVEL = 4
@@ -51,12 +51,12 @@
 option CONFIG_COMPRESS = 1

romimage "image"
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=64*1024
-	option COREBOOT_EXTRA_VERSION=".0"
+	option USE_FALLBACK_IMAGE = 1
+	option ROM_IMAGE_SIZE = 64 * 1024
+	option COREBOOT_EXTRA_VERSION = ".0"
    payload ../payload.elf
    # If getting payload from IDE
-	#payload /dev/null
+	# payload /dev/null
 end

buildrom ./coreboot.rom ROM_SIZE "image"