Re: [coreboot] Query regarding coreboot for new intel customized board

[Naveed Ghori]

I believe the Valley Island design does not support DDR3 (only DDR-3L).
You are getting output from the serial port I assume based on your previous log.
Try the Gold4 FSP (debug version) to get more details on memory initialization.

From: Mayuri Tendulkar [mailto:[e-mail]]
Sent: Tuesday, 31 May 2016 12:39 PM
To: Naveed Ghori; Wim Vervoorn; Zoran Stojsavljevic
Cc: coreboot
Subject: RE: [coreboot] Query regarding coreboot for new intel customized board

Hi Naveed

Thanks for your inputs. But currently my board is not booting up.

Not sure what caused this. Last we flashed coreboot where I used Minnowboard Max reference, did changes for our design and patched TXE and descriptor file from reference bios of my board.

Currently DDR3 is in reset, so debugging that.

Regards
Mayuri

From: Naveed Ghori [mailto:[e-mail]]
Sent: 31 May 2016 07:22
To: Wim Vervoorn <[e-mail]>; Mayuri Tendulkar <[e-mail]>; Zoran Stojsavljevic <[e-mail]>
Cc: coreboot <[e-mail]>
Subject: RE: [coreboot] Query regarding coreboot for new intel customized board

Mayuri,
Not sure if you have gotten further but a few more suggestions:

-        As your board is based on Valley Island, use the Bayley bay as a base (I may be able to help more with that as that is what I used)

-        Initially Use FPS v4 as there is a debug version that gives some more output (especially about the RAM etc)

-        Use the correct memory. If you use the wrong type it will get stuck at the location you mentioned

-        Memory (DDR-3L, not DDR3). Best to use similar sticks to remove that as a possible obstacle

-        Get access the FITC tool if you do not have it. Ask your Intel rep.

-        For the Bayley bay you will need to modify at least the GPIO files to match your design (based on valley Island).

Best of luck,
Naveed Ghori

From: coreboot [mailto:[e-mail]] On Behalf Of Wim Vervoorn
Sent: Thursday, 26 May 2016 4:01 PM
To: Mayuri Tendulkar; Zoran Stojsavljevic
Cc: coreboot
Subject: Re: [coreboot] Query regarding coreboot for new intel customized board

Hello Zoran,

This is a nice suggestion but it doesn’t work as the system is not booting.

Best Regards,
Wim Vervoorn

Eltan B.V.
Ambachtstraat 23
5481 SM Schijndel
The Netherlands

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From: Mayuri Tendulkar [mailto:[e-mail]]
Sent: Thursday, May 26, 2016 8:57 AM
To: Zoran Stojsavljevic <[e-mail]>
Cc: Wim Vervoorn <[e-mail]>; coreboot <[e-mail]>
Subject: RE: [coreboot] Query regarding coreboot for new intel customized board

Thanks. I will check on this option.

I am trying putty only to check serial o/p.

From: Zoran Stojsavljevic [mailto:[e-mail]]
Sent: 26 May 2016 12:13
To: Mayuri Tendulkar <[e-mail]>
Cc: Wim Vervoorn <[e-mail]>; coreboot <[e-mail]>
Subject: Re: [coreboot] Query regarding coreboot for new intel customized board

Hello Mayuri,

You need to play (maybe, just a kludge) a bit with Coreboot "make menuconfig", and there with console setup:

[Inline image 1]

You also might want to install on your Linux distro PuTTY console (given UBUNTU apt-get and Fedora dnf commands), to set your Rx terminal correctly (at least, I know PuTTY well, always worked for me):

sudo apt-get/dnf install putty

Zoran

On Thu, May 26, 2016 at 6:33 AM, Mayuri Tendulkar <[e-mail]> wrote:
Thanks Vim.

Currently I am not able to get any serial prints out on my reference board.

My board is based on Intel ISX board based on Baytrail-I soc E3825 given below.

https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluation...

I have built coreboot for this, but unable to get serial prints.

How I should debug this further.

Regards
Mayuri

From: Wim Vervoorn [mailto:[e-mail]]
Sent: 24 May 2016 13:26
To: Mayuri Tendulkar <[e-mail]>
Subject: Re: Query regarding coreboot for new intel customized board

Hello Mayuri,

If your rom image is the same it could be due to the lack of support for the flash device you are using. The MRC cache is preserved in flash so you need to be able to write it.

For the others the numbers etc you mention are informational for the OS. They are not strictly required but the OS builds a registry of the items it retrieves from the SMBIOS. If you don’t require this you could also disable the functionality.

Best Regards,
Wim Vervoorn

Eltan B.V.
Ambachtstraat 23
5481 SM Schijndel
The Netherlands

T : [phone]
E : [e-mail]
W : http://www.eltan.com
"THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE [phone]tel:%2B31-%280%2973-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES."

From: coreboot [mailto:[e-mail]] On Behalf Of Mayuri Tendulkar
Sent: Tuesday, May 24, 2016 7:26 AM
To: coreboot <[e-mail]>
Subject: [coreboot] Query regarding coreboot for new intel customized board

Hi team

I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB.

As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required.

If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found.

But if the same code changes I copied under  src/intel/mainboard/minnowmax and built, it booted fine.

I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax.

Is there some master registry where all these are stored, and if any new entry comes, how we should add it.

Regards
Mayuri

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