Author: mjones Date: 2008-07-23 23:11:20 +0200 (Wed, 23 Jul 2008) New Revision: 3434
Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000083.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000084.h Removed: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000066.h Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb Log: Update to the latest AMD Fam10 microcode patches. Add platform option for patch file name.
Signed-off-by: Marc Jones marc.jones@amd.com Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2008-07-23 21:04:03 UTC (rev 3433) +++ trunk/coreboot-v2/src/config/Options.lb 2008-07-23 21:11:20 UTC (rev 3434) @@ -1061,6 +1061,12 @@ comment "use AMD MCT to init RAM instead of native code" end
+define AMD_UCODE_PATCH_FILE + default none + export used + format ""%s"" + comment "name of the micorcode patch file" + define CONFIG_VIDEO_MB default none export used
Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h 2008-07-23 21:04:03 UTC (rev 3433) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h 2008-07-23 21:11:20 UTC (rev 3434) @@ -1,164 +0,0 @@ -/* - ============================================================ - (c) Advanced Micro Devices, Inc., 2004-2008 - - The enclosed microcode is intended to be used with AMD - Microprocessors. You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes - acknowledgement of AMD's proprietary rights in them. - ============================================================ -*/ - - -0x08, 0x20, 0x11, 0x01, 0x65, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, -0x9B, 0x78, 0x67, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x22, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, -0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, -0xAA, 0x0B, 0x00, 0x00, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, -0x9A, 0x0B, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, -0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, -0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, -0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, -0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, -0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, -0xC0, 0xCF, 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Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000066.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000066.h 2008-07-23 21:04:03 UTC (rev 3433) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000066.h 2008-07-23 21:11:20 UTC (rev 3434) @@ -1,164 +0,0 @@ -/* - ============================================================ - (c) Advanced Micro Devices, Inc., 2004-2008 - - The enclosed microcode is intended to be used with AMD - Microprocessors. You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes - acknowledgement of AMD's proprietary rights in them. - ============================================================ -*/ - - -0x08, 0x20, 0x11, 0x01, 0x66, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, -0x83, 0x75, 0xF0, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x20, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, -0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, -0xFF, 0xFF, 0xFF, 0xFF, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, -0x9A, 0x0B, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, -0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, -0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, -0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, -0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, -0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, -0xC0, 0xCF, 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Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000083.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000083.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000083.h 2008-07-23 21:11:20 UTC (rev 3434) @@ -0,0 +1,165 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2008 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + + +0x08, 0x20, 0x30, 0x04, 0x83, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0xA8, 0x88, 0x43, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x22, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, +0xAA, 0x0B, 0x00, 0x00, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, +0x70, 0x0C, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, +0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, +0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, +0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, +0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, +0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, +0xC0, 0xCF, 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Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000084.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000084.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000084.h 2008-07-23 21:11:20 UTC (rev 3434) @@ -0,0 +1,165 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2008 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + + +0x08, 0x20, 0x01, 0x05, 0x84, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x90, 0x85, 0xCC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x20, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, +0xFF, 0xFF, 0xFF, 0xFF, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, +0x70, 0x0C, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, +0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, +0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, +0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, +0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, +0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, +0xC0, 0xCF, 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Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c 2008-07-23 21:04:03 UTC (rev 3433) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c 2008-07-23 21:11:20 UTC (rev 3434) @@ -31,15 +31,23 @@
#ifdef __ROMCC__
- // Barcelona rev Ax -// #include "mc_patch_01000020.h" +/* From the Revision Guide : + * Equivalent Processor Table for AMD Family 10h Processors + * + * Installed Processor Equivalent Processor Patch Level + * Revision ID Revision ID + * 00100F00h 1000h 01000020h + * 00100F01h 1000h 01000020h + * 00100F02h 1000h 01000020h + * 00100F20h 1020h 01000084h + * 00100F21h 1020h 01000084h + * 00100F2Ah 1020h 01000084h + * 00100F22h 1022h 01000083h + * 00100F23h 1022h 01000083h + */
- // Barcelona rev B0, B1, BA -// #include "mc_patch_01000066.h" +#include AMD_UCODE_PATCH_FILE
- // Barcelona rev B2, B3 - #include "mc_patch_01000065.h" - #endif /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0,
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2008-07-23 21:04:03 UTC (rev 3433) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2008-07-23 21:11:20 UTC (rev 3434) @@ -114,6 +114,7 @@
uses CONFIG_USE_PRINTK_IN_CAR uses CAR_FAM10 +uses AMD_UCODE_PATCH_FILE
### ### Build options @@ -260,6 +261,15 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+## +## Set microcode patch file name +## +## Barcelona rev Ax: "mc_patch_01000020.h" +## Barcelona rev B0, B1, BA: "mc_patch_01000084.h" +## Barcelona rev B2, B3: "mc_patch_01000083.h" +## +default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h" + ### ### coreboot layout values ###