Re: [coreboot] apologies in advance for a question I may have asked

[Carl-Daniel Hailfinger]

Am 27.08.2014 22:07 schrieb ron minnich:
> well, stefan, I was hoping not to hear that answer, but I guess that's
> the way it goes :-)

Well, 16 MByte are doable and also happen on real hardware, but with
bigger chips you're out of luck. Both for SPI addressing reasons (24 bit
addresses by default) and for legacy reasons. I heard rumors that newer
x86 can handle larger flash chips, but AFAIK only with the help of PIO,
not directly mapped. Similar rule for Qemu.

That said, changing FLASH_MAP_BASE_MIN to

#define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 16*1024*1024))

should work.

Regards,
Carl-Daniel

apologies in advance for a question I may have asked

[ron minnich]

turns out 16 MiB will do it!

Thanks all! I really am glad you are here to answer silly questions :-)

ron

On Thu, Aug 28, 2014 at 1:29 PM, Carl-Daniel Hailfinger
 wrote:
> Am 27.08.2014 22:07 schrieb ron minnich:
> > well, stefan, I was hoping not to hear that answer, but I guess that's
> > the way it goes :-)
>
> Well, 16 MByte are doable and also happen on real hardware, but with
> bigger chips you're out of luck. Both for SPI addressing reasons (24 bit
> addresses by default) and for legacy reasons. I heard rumors that newer
> x86 can handle larger flash chips, but AFAIK only with the help of PIO,
> not directly mapped. Similar rule for Qemu.
>
> That said, changing FLASH_MAP_BASE_MIN to
>
> #define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 16*1024*1024))
>
> should work.
>
> Regards,
> Carl-Daniel