-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256
On 05/17/2018 02:11 PM, Banik, Subrata wrote:
Subrata,
[Subrata] this specific issue, we haven't seen on any KBL/SKL system we have. I can double confirm this value tomorrow. For now, please try to check if increasing timeout is helping or not?
Values tried: - - vmx: 2x, sgx: 28x: https://pastebin.com/imRJk7Y8 - - vmx: 4x, sgx: 14x: https://pastebin.com/Rwvcs4XE - - vmx: 8x, sgx: 14x: https://pastebin.com/TLavR6CN - - vmx: 2x, sgx: 28x: https://pastebin.com/SdbP0RdG - - vmx: 32x, sgx: 56x: https://pastebin.com/NsK25Lm5
Not much chageing. Mostly timing of SIPI completion and order of SMRAM relocation.
Btw, Can you please send me a complete serial log for my analysis.
Sure: - - my code base: https://pastebin.com/fRFZTx10 - - with 26286/3: https://pastebin.com/S1n5S8df
I believe this should not be relevant, but I don't have serial enabled and all logs are dumped to SPI. I'm not sure if SPI controller interrupts may affect this anyhow.
Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com
Can you please check few more things and please help to clarify some details.
1. Is this kind of regression ? because we are not seeing this issue. 2. I believe its FSP1.1 selection in Kconfig, please confirm ? 3. Please check if BIOS_RESET_CPL is already set prior to setting 0x121 MSR Refer to code enable_bios_reset_cpl As per my debug MSR 0x121 will only through exception if BIOS reset cpl done bits are already set before this call, which shouldn't be the case, otherwise all SKL design might see this issue.
Thanks, Subrata
-----Original Message----- From: Piotr Król [mailto:piotr.krol@3mdeb.com] Sent: Thursday, May 17, 2018 7:09 PM To: Banik, Subrata subrata.banik@intel.com Cc: coreboot@coreboot.org Subject: Re: Exception on Skylake after enabling ACPI timer emulation
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256
On 05/17/2018 02:11 PM, Banik, Subrata wrote:
Subrata,
[Subrata] this specific issue, we haven't seen on any KBL/SKL system we have. I can double confirm this value tomorrow. For now, please try to check if increasing timeout is helping or not?
Values tried: - - vmx: 2x, sgx: 28x: https://pastebin.com/imRJk7Y8 - - vmx: 4x, sgx: 14x: https://pastebin.com/Rwvcs4XE - - vmx: 8x, sgx: 14x: https://pastebin.com/TLavR6CN - - vmx: 2x, sgx: 28x: https://pastebin.com/SdbP0RdG - - vmx: 32x, sgx: 56x: https://pastebin.com/NsK25Lm5
Not much chageing. Mostly timing of SIPI completion and order of SMRAM relocation.
Btw, Can you please send me a complete serial log for my analysis.
Sure: - - my code base: https://pastebin.com/fRFZTx10 - - with 26286/3: https://pastebin.com/S1n5S8df
I believe this should not be relevant, but I don't have serial enabled and all logs are dumped to SPI. I'm not sure if SPI controller interrupts may affect this anyhow.
Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com
-
Banik, Subrata -
Piotr Król