When I boot coreboot (the alix2 image) on a 6F2 I get the following spew.
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Changing serial settings was 13/5 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot WARNING - Timeout at i8042_wait_write:51!
coreboot-4.0-1936-g33dd7a8-dirty Wed Jan 4 12:20:50 MST 2012 starting... MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:0000182e Configuring PLL.
coreboot-4.0-1936-g33dd7a8-dirty Wed Jan 4 12:20:50 MST 2012 starting... MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:07de002e PLL configured. Castle 2.0 BTM periodic sync period. Enable Quack for fewer re-RAS on the MC GLIU port active enable Set the Delay Control in GLCP spd_read_byte dev 50 addr 0d returns 08 spd_read_byte dev 50 addr 05 returns 01 spd_read_byte dev 51 returns 0xff Enable RSDC FPU imprecise exceptions bit Enable Suspend on HLT & PAUSE instructions Enable SUSP and allow TSC to run in Suspend Setup throttling delays to proper mode Done cpuRegInit Ram1.00 Ram2.00 * sdram_set_spd_register spd_read_byte dev 50 addr 15 returns ff * Check DIMM 0 * Check DIMM 1 spd_read_byte dev 51 returns 0xff * Check DDR MAX spd_read_byte dev 50 addr 09 returns 0a spd_read_byte dev 51 returns 0xff * AUTOSIZE DIMM 0 * Check present spd_read_byte dev 50 addr 02 returns 07 * MODBANKS spd_read_byte dev 50 addr 05 returns 01 * FIELDBANKS spd_read_byte dev 50 addr 11 returns 04 * SPDNUMROWS spd_read_byte dev 50 addr 03 returns 03 spd_read_byte dev 50 addr 04 returns 0a * SPDBANKDENSITY spd_read_byte dev 50 addr 1f returns 40 * DIMMSIZE * BEFORT CTZ * TEST DIMM SIZE>8 * PAGESIZE spd_read_byte dev 50 addr 04 returns 0a * MAXCOLADDR * >12address test * RDMSR CF07 * WRMSR CF07 * ALL DONE * AUTOSIZE DIMM 1 * Check present spd_read_byte dev 51 returns 0xff * set cas latency spd_read_byte dev 50 addr 12 returns 10 spd_read_byte dev 50 addr 17 returns 3c spd_read_byte dev 50 addr 19 returns 4b spd_read_byte dev 51 returns 0xff * set all latency spd_read_byte dev 50 addr 1e returns 28 spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1b returns 0f spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1d returns 0f spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1c returns 0a spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 2a returns 46 spd_read_byte dev 51 returns 0xff * set emrs spd_read_byte dev 50 addr 16 returns ff spd_read_byte dev 51 returns 0xff * set ref rate spd_read_byte dev 50 addr 0c returns 3a spd_read_byte dev 51 returns 0xff Ram3 * DRAM controller init done.
RAM DLL lock Ram4 POST 02 Past wbinvd Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-1936-g33dd7a8-dirty Wed Jan 4 12:20:50 MST 2012 booting... clocks_per_usec: 499 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 Compare with tree... Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 scan_static_bus for Root Device
Entering northbridge.c: enable_dev with path 6 Entering northbridge.c: pci_domain_enable
Enter northbridge_init_early writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB SysmemInit: enable for 256MBytes usable RAM: 268304383 bytes SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB SMMGL0Init: 268304384 bytes SMMGL0Init: offset is 0x80400000 SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0 writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB SysmemInit: enable for 256MBytes usable RAM: 268304383 bytes SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100 SMMGL1Init: SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0 writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00 CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 L2 cache enabled Enabling cache GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000 GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000 Exit northbridge_init_early Done cpubug fixes Not Doing ChipsetFlashSetup() Preparing for VSA... VSA: Real mode stub @00000600: 862 bytes Searching for vsa Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Stage: loading vsa @ 0x60000 (57504 bytes), entry @ 0x60020 Stage: done loading. VSA: Buffer @00060000 *[0k]=ba VSA: Signature *[0x20-0x23] is b0:10:e6:80 Calling VSA module... ... VSA module returned. VSM: VSA2 VR signature verified. Graphics init... VRC_VG value: 0x2808 Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled
Entering northbridge.c: enable_dev with path 7
APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00
Entering northbridge.c: enable_dev with path 2
PCI: 00:01.0 [1022/2080] ops PCI: 00:01.0 [1022/2080] enabled
Entering northbridge.c: enable_dev with path 2
PCI: 00:01.1 [1022/2081] enabled PCI: 00:01.2 [1022/2082] enabled PCI: 00:09.0 [1106/3053] enabled PCI: 00:0a.0 [1106/3053] enabled PCI: 00:0c.0 [168c/0013] enabled cs5536: southbridge_enable: dev is 00112660 PCI: 00:0f.0 [1022/2090] bus ops PCI: 00:0f.0 [1022/2090] enabled cs5536: southbridge_enable: dev is 001126a8 PCI: Static device PCI: 00:0f.1 not found, disabling it. cs5536: southbridge_enable: dev is 001126f0 PCI: 00:0f.2 [1022/209a] ops PCI: 00:0f.2 [1022/209a] enabled PCI: 00:0f.3 [1022/2093] enabled cs5536: southbridge_enable: dev is 00112738 PCI: 00:0f.4 [1022/2094] enabled cs5536: southbridge_enable: dev is 00112780 PCI: 00:0f.5 [1022/2095] enabled PCI: 00:0f.6 [1022/2096] enabled PCI: 00:0f.7 [1022/2097] enabled scan_static_bus for PCI: 00:0f.0 scan_static_bus for PCI: 00:0f.0 done PCI: pci_scan_bus returning with max=000 scan_static_bus for Root Device done done Setting up VGA for PCI: 00:01.1 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:01.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 10 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 18 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 20 PCI: 00:01.2 PCI: 00:01.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:09.0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI: 00:0a.0 PCI: 00:0a.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:0a.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 10 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 18 PCI: 00:0f.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 1c PCI: 00:0f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 20 PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:0f.1 PCI: 00:0f.2 PCI: 00:0f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:0f.3 PCI: 00:0f.3 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 PCI: 00:0f.4 PCI: 00:0f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0f.5 PCI: 00:0f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0f.6 PCI: 00:0f.6 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10 PCI: 00:0f.7 PCI: 00:0f.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:09.0 10 * [0x0 - 0xff] io PCI: 00:0a.0 10 * [0x400 - 0x4ff] io PCI: 00:0f.0 14 * [0x800 - 0x8ff] io PCI: 00:0f.0 20 * [0xc00 - 0xc7f] io PCI: 00:0f.3 10 * [0xc80 - 0xcff] io PCI: 00:0f.0 18 * [0x1000 - 0x103f] io PCI: 00:0f.0 24 * [0x1040 - 0x107f] io PCI: 00:0f.0 1c * [0x1080 - 0x109f] io PCI: 00:0f.2 20 * [0x10a0 - 0x10af] io PCI: 00:0f.0 10 * [0x10b0 - 0x10b7] io PCI: 00:01.0 10 * [0x10b8 - 0x10bb] io PCI_DOMAIN: 0000 compute_resources_io: base: 10bc size: 10bc align: 8 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.1 10 * [0x0 - 0xffffff] mem PCI: 00:0c.0 10 * [0x1000000 - 0x100ffff] mem PCI: 00:01.1 14 * [0x1010000 - 0x1013fff] mem PCI: 00:01.1 18 * [0x1014000 - 0x1017fff] mem PCI: 00:01.1 1c * [0x1018000 - 0x101bfff] mem PCI: 00:01.1 20 * [0x101c000 - 0x101ffff] mem PCI: 00:01.2 10 * [0x1020000 - 0x1023fff] mem PCI: 00:0f.6 10 * [0x1024000 - 0x1025fff] mem PCI: 00:0f.4 10 * [0x1026000 - 0x1026fff] mem PCI: 00:0f.5 10 * [0x1027000 - 0x1027fff] mem PCI: 00:0f.7 10 * [0x1028000 - 0x1028fff] mem PCI: 00:09.0 14 * [0x1029000 - 0x10290ff] mem PCI: 00:0a.0 14 * [0x1029100 - 0x10291ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 1029200 size: 1029200 align: 24 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:01.2 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0a.0 constrain_resources: PCI: 00:0c.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.2 constrain_resources: PCI: 00:0f.3 constrain_resources: PCI: 00:0f.4 constrain_resources: PCI: 00:0f.5 constrain_resources: PCI: 00:0f.6 constrain_resources: PCI: 00:0f.7 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:10bc align:8 gran:0 limit:ffff Assigned: PCI: 00:09.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:0a.0 10 * [0x1400 - 0x14ff] io Assigned: PCI: 00:0f.0 14 * [0x1800 - 0x18ff] io Assigned: PCI: 00:0f.0 20 * [0x1c00 - 0x1c7f] io Assigned: PCI: 00:0f.3 10 * [0x1c80 - 0x1cff] io Assigned: PCI: 00:0f.0 18 * [0x2000 - 0x203f] io Assigned: PCI: 00:0f.0 24 * [0x2040 - 0x207f] io Assigned: PCI: 00:0f.0 1c * [0x2080 - 0x209f] io Assigned: PCI: 00:0f.2 20 * [0x20a0 - 0x20af] io Assigned: PCI: 00:0f.0 10 * [0x20b0 - 0x20b7] io Assigned: PCI: 00:01.0 10 * [0x20b8 - 0x20bb] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 20bc size: 10bc align: 8 gran: 0 done PCI_DOMAIN: 0000 allocate_resources_mem: base:fd000000 size:1029200 align:24 gran:0 limit:febfffff Assigned: PCI: 00:01.1 10 * [0xfd000000 - 0xfdffffff] mem Assigned: PCI: 00:0c.0 10 * [0xfe000000 - 0xfe00ffff] mem Assigned: PCI: 00:01.1 14 * [0xfe010000 - 0xfe013fff] mem Assigned: PCI: 00:01.1 18 * [0xfe014000 - 0xfe017fff] mem Assigned: PCI: 00:01.1 1c * [0xfe018000 - 0xfe01bfff] mem Assigned: PCI: 00:01.1 20 * [0xfe01c000 - 0xfe01ffff] mem Assigned: PCI: 00:01.2 10 * [0xfe020000 - 0xfe023fff] mem Assigned: PCI: 00:0f.6 10 * [0xfe024000 - 0xfe025fff] mem Assigned: PCI: 00:0f.4 10 * [0xfe026000 - 0xfe026fff] mem Assigned: PCI: 00:0f.5 10 * [0xfe027000 - 0xfe027fff] mem Assigned: PCI: 00:0f.7 10 * [0xfe028000 - 0xfe028fff] mem Assigned: PCI: 00:09.0 14 * [0xfe029000 - 0xfe0290ff] mem Assigned: PCI: 00:0a.0 14 * [0xfe029100 - 0xfe0291ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe029200 size: 1029200 align: 24 gran: 0 done Root Device assign_resources, bus 0 link: 0
Entering northbridge.c: pci_domain_set_resources
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 mem PCI: 00:01.1 14 <- [0x00fe010000 - 0x00fe013fff] size 0x00004000 gran 0x0e mem PCI: 00:01.1 18 <- [0x00fe014000 - 0x00fe017fff] size 0x00004000 gran 0x0e mem PCI: 00:01.1 1c <- [0x00fe018000 - 0x00fe01bfff] size 0x00004000 gran 0x0e mem PCI: 00:01.1 20 <- [0x00fe01c000 - 0x00fe01ffff] size 0x00004000 gran 0x0e mem PCI: 00:01.2 10 <- [0x00fe020000 - 0x00fe023fff] size 0x00004000 gran 0x0e mem PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:09.0 14 <- [0x00fe029000 - 0x00fe0290ff] size 0x00000100 gran 0x08 mem PCI: 00:0a.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:0a.0 14 <- [0x00fe029100 - 0x00fe0291ff] size 0x00000100 gran 0x08 mem PCI: 00:0c.0 10 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 mem PCI: 00:0f.0 10 <- [0x00000020b0 - 0x00000020b7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io PCI: 00:0f.0 18 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io PCI: 00:0f.0 1c <- [0x0000002080 - 0x000000209f] size 0x00000020 gran 0x05 io PCI: 00:0f.0 20 <- [0x0000001c00 - 0x0000001c7f] size 0x00000080 gran 0x07 io PCI: 00:0f.0 24 <- [0x0000002040 - 0x000000207f] size 0x00000040 gran 0x06 io PCI: 00:0f.2 20 <- [0x00000020a0 - 0x00000020af] size 0x00000010 gran 0x04 io PCI: 00:0f.3 10 <- [0x0000001c80 - 0x0000001cff] size 0x00000080 gran 0x07 io PCI: 00:0f.4 10 <- [0x00fe026000 - 0x00fe026fff] size 0x00001000 gran 0x0c mem PCI: 00:0f.5 10 <- [0x00fe027000 - 0x00fe027fff] size 0x00001000 gran 0x0c mem PCI: 00:0f.6 10 <- [0x00fe024000 - 0x00fe025fff] size 0x00002000 gran 0x0d mem PCI: 00:0f.7 10 <- [0x00fe028000 - 0x00fe028fff] size 0x00001000 gran 0x0c mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:01.0 PCI_DOMAIN: 0000 resource base 1000 size 10bc align 8 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base fd000000 size 1029200 align 24 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size f720000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:01.0 PCI: 00:01.0 resource base 20b8 size 4 align 2 gran 2 limit ffff flags 40000100 index 10 PCI: 00:01.1 PCI: 00:01.1 resource base fd000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10 PCI: 00:01.1 resource base fe010000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 14 PCI: 00:01.1 resource base fe014000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 18 PCI: 00:01.1 resource base fe018000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 1c PCI: 00:01.1 resource base fe01c000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 20 PCI: 00:01.2 PCI: 00:01.2 resource base fe020000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 10 PCI: 00:09.0 PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 00:09.0 resource base fe029000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 PCI: 00:0a.0 PCI: 00:0a.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 00:0a.0 resource base fe029100 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 PCI: 00:0c.0 PCI: 00:0c.0 resource base fe000000 size 10000 align 16 gran 16 limit febfffff flags 60000200 index 10 PCI: 00:0f.0 PCI: 00:0f.0 resource base 20b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:0f.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags 60000100 index 14 PCI: 00:0f.0 resource base 2000 size 40 align 6 gran 6 limit ffff flags 60000100 index 18 PCI: 00:0f.0 resource base 2080 size 20 align 5 gran 5 limit ffff flags 60000100 index 1c PCI: 00:0f.0 resource base 1c00 size 80 align 7 gran 7 limit ffff flags 60000100 index 20 PCI: 00:0f.0 resource base 2040 size 40 align 6 gran 6 limit ffff flags 60000100 index 24 PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:0f.1 PCI: 00:0f.2 PCI: 00:0f.2 resource base 20a0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:0f.3 PCI: 00:0f.3 resource base 1c80 size 80 align 7 gran 7 limit ffff flags 60000100 index 10 PCI: 00:0f.4 PCI: 00:0f.4 resource base fe026000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:0f.5 PCI: 00:0f.5 resource base fe027000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:0f.6 PCI: 00:0f.6 resource base fe024000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 10 PCI: 00:0f.7 PCI: 00:0f.7 resource base fe028000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 Done allocating resources. Enabling resources... PCI: 00:01.0 cmd <- 05 PCI: 00:01.1 subsystem <- 0000/0000 PCI: 00:01.1 cmd <- 03 PCI: 00:01.2 cmd <- 02 PCI: 00:09.0 cmd <- 83 PCI: 00:0a.0 cmd <- 83 PCI: 00:0c.0 cmd <- 02 PCI: 00:0f.0 cmd <- 09 PCI: 00:0f.2 cmd <- 01 PCI: 00:0f.3 cmd <- 01 PCI: 00:0f.4 subsystem <- 0000/0000 PCI: 00:0f.4 cmd <- 02 PCI: 00:0f.5 subsystem <- 0000/0000 PCI: 00:0f.5 cmd <- 02 PCI: 00:0f.6 cmd <- 02 PCI: 00:0f.7 cmd <- 02 done. Initializing devices... Root Device init ALIX.2D ENTER init ALIX.2D EXIT init APIC_CLUSTER: 0 init
Entering northbridge.c: cpu_bus_init
Initializing CPU #0 CPU: vendor AMD device 5a2 CPU: family 05, model 0a, stepping 02 model_lx_init Enabling cache A20 (0x92): 2 A20 (0x92): 2 CPU model_lx_init DONE CPU #0 initialized PCI: 00:01.0 init
Entering northbridge.c: northbridge_init
PCI: 00:01.1 init Searching for pci1022,2081.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2081.rom'. PCI: 00:01.2 init Searching for pci1022,2082.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2082.rom'. PCI: 00:09.0 init Searching for pci1106,3053.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1106,3053.rom'. PCI: 00:0a.0 init Searching for pci1106,3053.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1106,3053.rom'. PCI: 00:0c.0 init Searching for pci168c,0013.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci168c,0013.rom'. PCI: 00:0f.0 init cs5536: southbridge_init RTC Init GPIO_ADDR: 00001800 uarts_init: enable COM1 uarts_init: enable COM2 uarts_init: wrote COM2 address 0x2f8 uarts_init: set COM2 irq uarts_init: set output enable uarts_init: set OUTAUX1 uarts_init: set pullup COM2 uarts_init: COM2 enabled cs5536: southbridge_init: enable_ide_nand_flash is 0 Disabling VPCI device: 0x80000900 Disabling VPCI device: 0x80007B00 PCI: 00:0f.2 init cs5536_ide: ide_init PCI: 00:0f.3 init Searching for pci1022,2093.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2093.rom'. PCI: 00:0f.4 init Searching for pci1022,2094.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2094.rom'. PCI: 00:0f.5 init Searching for pci1022,2095.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2095.rom'. PCI: 00:0f.6 init Searching for pci1022,2096.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2096.rom'. PCI: 00:0f.7 init Searching for pci1022,2097.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check vsa Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'pci1022,2097.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 0 PCI: 00:0f.2: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI: 00:01.2: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0f.3: enabled 1 PCI: 00:0f.6: enabled 1 PCI: 00:0f.7: enabled 1 CPU: 00: enabled 1 Initializing CBMEM area to 0xf7d0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 0f7d0200...ok High Tables Base is f7d0000. Copying Interrupt Routing Table to 0x000f0000... done. PIRQ Entry 0 Dev/Fn: 1 Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:1.2 i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x800 PIRQ Entry 1 Dev/Fn: 9 Slot: 0 INT: A link: 2 bitmap: 400 IRQ: 10 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 10 to 0:9.0 i8259_configure_irq_trigger: current interrupts are 0x800 i8259_configure_irq_trigger: try to set interrupts 0xc00 PIRQ Entry 2 Dev/Fn: A Slot: 0 INT: A link: 3 bitmap: 800 IRQ: 11 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:a.0 i8259_configure_irq_trigger: current interrupts are 0xc00 i8259_configure_irq_trigger: try to set interrupts 0xc00 PIRQ Entry 3 Dev/Fn: B Slot: 0 INT: A link: 4 bitmap: 200 IRQ: 9 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed PIRQ Entry 4 Dev/Fn: C Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 400 IRQ: 10 INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:c.0 i8259_configure_irq_trigger: current interrupts are 0xc00 i8259_configure_irq_trigger: try to set interrupts 0xc00 PIRQ Entry 5 Dev/Fn: E Slot: 0 INT: A link: 3 bitmap: 800 IRQ: 11 INT: B link: 4 bitmap: 200 IRQ: 9 INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed PIRQ Entry 6 Dev/Fn: F Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 400 IRQ: 10 INT: C link: 3 bitmap: 800 IRQ: 11 INT: D link: 4 bitmap: 200 IRQ: 9 Assigning IRQ 9 to 0:f.4 i8259_configure_irq_trigger: current interrupts are 0xc00 i8259_configure_irq_trigger: try to set interrupts 0xe00 Assigning IRQ 9 to 0:f.5 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ1: 11 PIRQ2: 10 PIRQ3: 11 PIRQ4: 9 Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x0f7d0400... done. PIRQ Entry 0 Dev/Fn: 1 Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:1.2 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ Entry 1 Dev/Fn: 9 Slot: 0 INT: A link: 2 bitmap: 400 IRQ: 10 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 10 to 0:9.0 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ Entry 2 Dev/Fn: A Slot: 0 INT: A link: 3 bitmap: 800 IRQ: 11 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:a.0 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ Entry 3 Dev/Fn: B Slot: 0 INT: A link: 4 bitmap: 200 IRQ: 9 INT: B link: 0 bitmap: 0 not routed INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed PIRQ Entry 4 Dev/Fn: C Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 400 IRQ: 10 INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed Assigning IRQ 11 to 0:c.0 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ Entry 5 Dev/Fn: E Slot: 0 INT: A link: 3 bitmap: 800 IRQ: 11 INT: B link: 4 bitmap: 200 IRQ: 9 INT: C link: 0 bitmap: 0 not routed INT: D link: 0 bitmap: 0 not routed PIRQ Entry 6 Dev/Fn: F Slot: 0 INT: A link: 1 bitmap: 800 IRQ: 11 INT: B link: 2 bitmap: 400 IRQ: 10 INT: C link: 3 bitmap: 800 IRQ: 11 INT: D link: 4 bitmap: 200 IRQ: 9 Assigning IRQ 9 to 0:f.4 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 Assigning IRQ 9 to 0:f.5 i8259_configure_irq_trigger: current interrupts are 0xe00 i8259_configure_irq_trigger: try to set interrupts 0xe00 PIRQ1: 11 PIRQ2: 10 PIRQ3: 11 PIRQ4: 9 PIRQ table: 144 bytes. Adding CBMEM entry as no. 3 smbios_write_tables: 0f7d1400 Root Device (PC Engines ALIX.2D Mainboard) PCI_DOMAIN: 0000 (AMD LX Northbridge) PCI: 00:01.0 (AMD LX Northbridge) PCI: 00:01.1 (AMD LX Northbridge) PCI: 00:0f.0 (AMD Geode CS5536 Southbridge) PCI: 00:0f.1 (AMD Geode CS5536 Southbridge) PCI: 00:0f.2 (AMD Geode CS5536 Southbridge) PCI: 00:0f.4 (AMD Geode CS5536 Southbridge) PCI: 00:0f.5 (AMD Geode CS5536 Southbridge) APIC_CLUSTER: 0 (AMD LX Northbridge) APIC: 00 () PCI: 00:01.2 () PCI: 00:09.0 () PCI: 00:0a.0 () PCI: 00:0c.0 () PCI: 00:0f.3 () PCI: 00:0f.6 () PCI: 00:0f.7 () CPU: 00 () SMBIOS tables: 297 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum d461 New low_table_end: 0x00000518 Now going to write high coreboot table at 0x0f7d1c00 rom_table_end = 0x0f7d1c00 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x0f7d1c00 to 0x0f7e0000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000000f7cffff: RAM 3. 000000000f7d0000-000000000f7dffff: CONFIGURATION TABLES Wrote coreboot table at: 0f7d1c00 - 0f7d1dcc checksum b828 coreboot table: 460 bytes. Multiboot Information structure has been written. 0. FREE SPACE 0f7d3c00 0000c400 1. GDT 0f7d0200 00000200 2. IRQ TABLE 0f7d0400 00001000 3. SMBIOS 0f7d1400 00000800 4. COREBOOT 0f7d1c00 00002000 Searching for fallback/payload Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xfff8bcb8 data (compression=1) New segment dstaddr 0xe7e04 memsize 0x181fc srcaddr 0xfff8bcf0 filesize 0xc20b (cleaned up) New segment addr 0xe7e04 size 0x181fc offset 0xfff8bcf0 filesize 0xc20b Loading segment from rom address 0xfff8bcd4 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c20b lb: [0x0000000000100000, 0x0000000000124000) Post relocation: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c20b using LZMA [ 0x000e7e04, 00100000, 0x00100000) <- fff8bcf0 dest 000e7e04, end 00100000, bouncebuffer f788000 Loaded segments Jumping to boot code at fc8c0 entry = 0x000fc8c0 lb_start = 0x00100000 lb_size = 0x00024000 adjust = 0x0f6ac000 buffer = 0x0f788000 elf_boot_notes = 0x001127c8 adjusted_boot_notes = 0x0f7be7c8 Start bios (version 1.6.3-20120104_122101-builder) Found mainboard PC Engines ALIX.6 Found CBFS header at 0xfffffd30 Ram Size=0x0f7d0000 (0x0000000000000000 high) Relocating init from 0x000e8450 to 0x0f7b57a0 (size 42812) CPU Mhz=498 Found 9 PCI devices (max PCI bus is 00) No apic - only the main cpu is present. Copying SMBIOS entry point from 0x0f7d1400 to 0x000fdbd0 Scan for VGA option rom EHCI init on dev 00:0f.5 (regs=0xfe027010) WARNING - Timeout at i8042_flush:69! Found 0 lpt ports Found 2 serial ports ATA controller 1 at 1f0/3f4/0 (irq 14 dev 7a) ATA controller 2 at 170/374/0 (irq 15 dev 7a) ata0-0: SanDisk SDCFH-002G ATA-4 Hard-Disk (1907 MiBytes) Searching bootorder for: /pci@i0cf8/*@f,2/drive@0/disk@0 All threads complete. Scan for option roms Press F12 for boot menu.
drive 0x000fdb80: PCHS=3875/16/63 translation=large LCHS=968/64/63 s=3906560 Returned 65536 bytes of ZoneHigh e820 map has 5 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000000f7d0000 = 1 RAM 4: 000000000f7d0000 - 000000000f7e0000 = 2 RESERVED enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00 Press any key to continue. Press any key to continue.
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And then the linux early-printk logging begins.
Peter suggests it's an issue with the MTRR not being set up correctly (for caching), and is the same problem.
I'm seeing a 27-second pause after this line:
Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000
Also, the Alix 6F2 doesn't have a keyboard controller... is there a way to turn off the i8042 stuff?
Thanks,
-Philip
On Thu, Jan 5, 2012 at 6:56 PM, Philip Prindeville philipp_subx@redfish-solutions.com wrote:
Also, the Alix 6F2 doesn't have a keyboard controller... is there a way to turn off the i8042 stuff?
it used to be as simple as not putting pc80/keyboard or some such in the mainboard Config. I'll look tomorrow if I get time.
ron
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Philip Prindeville -
ron minnich