On Wednesday, May 7, 2003, at 03:06 PM, ron minnich wrote:
what is your southbridge part? can you look at the part directly?
So I have the datasheet for the 5595 now (found using google so not sure whether I should send it to you) um either way to enable flash they talk about using the
"address and data port, i.e. Port 70h and 71h, respectively. The access control with which the three portions of registers can be appropriately addressed are stored in PCI-ISA: 45h[3] (EXTEND_EN bit) and PCI-ISA: 45h[1](APCREG_EN bit)." but in the sis530 docs I get this for registers 70h:
"Register 70h to register 76h define the attribute of the Shadow RAM from 640 KBytes to 1 MBytes. All of the registers 70h to 75h are defined as below, and each register defines the corresponding memory segment's attribute which are listed in the following table. REGISTER DEFINED RANGE REGISTER DEFINED RANGE Register 70h bits 7:5 0C0000h-0C3FFFh Register 73h bits 7:5 0D8000h-0DBFFFh"
so I'm not sure how to set that in the 5595..? There must be some way through the pci bridge I think, but don't really know what I'm doing... so some pointers (or even pointers to some docs on how things work) would be great.
Register 45h (on the 5595) controls the flash writability. But on the sis530 45h is "IDE Secondary Channel/Master Drive Data Active Time Control" so again it is a matter of knowing how to communicate with the 5595 instead of the main chipset.
Now this is all great and what not, but I'm confused. We're having problems detecting the flash, not writing to it. So I'm not sure how this will help. As well in the flash_rom sources the enable_sis is never called.
In going over the sources to devbios and the flash_rom, I realize that I don't know anything much about the pci/isa bridges and such...
So basically I'm wondering what the next step is. 1) Does the write enable bit help with detecting? 2) Where do I get docs about how the pci & isa communication happens? 2a) do I need those docs?
that's about it...
On Thu, 8 May 2003, Nathanael Noblet wrote:
So I have the datasheet for the 5595 now (found using google so not sure whether I should send it to you) um either way to enable flash they talk about using the
send me the URL.
"Register 70h to register 76h define the attribute of the Shadow RAM from 640 KBytes to 1 MBytes. All of the registers 70h to 75h are defined as below, and each register defines the corresponding memory segment's attribute which are listed in the following table. REGISTER DEFINED RANGE REGISTER DEFINED RANGE Register 70h bits 7:5 0C0000h-0C3FFFh Register 73h bits 7:5 0D8000h-0DBFFFh"
not needed.
Register 45h (on the 5595) controls the flash writability. But on the sis530 45h is "IDE Secondary Channel/Master Drive Data Active Time Control" so again it is a matter of knowing how to communicate with the 5595 instead of the main chipset.
I think I need to see the doc.
Now this is all great and what not, but I'm confused. We're having problems detecting the flash, not writing to it. So I'm not sure how this will help. As well in the flash_rom sources the enable_sis is never called.
the reason is that you can't ID a flash without having write access to it.
- Does the write enable bit help with detecting?
it is essential. Must have it.
- Where do I get docs about how the pci & isa communication happens? 2a) do I need those docs?
send me the URL first. If it's legal to look at the doc I will take a look.
ron
On Thu, May 08, 2003 at 10:42:52AM -0600, ron minnich wrote:
On Thu, 8 May 2003, Nathanael Noblet wrote:
Now this is all great and what not, but I'm confused. We're having problems detecting the flash, not writing to it. So I'm not sure how this will help. As well in the flash_rom sources the enable_sis is never called.
the reason is that you can't ID a flash without having write access to it.
- Does the write enable bit help with detecting?
it is essential. Must have it.
To clarify this a bit;
Most flash ROM chips are identified, erased and programmed according to a standard set by JEDEC.
Byte-program, sector-erase, block-erase, chip-erase, software-id-entry and software-id-exit are the most common (the only?) commands available.
Each command is up to six write cycles long.
E.g. for byte-program:
Write 0xaah to address 0x5555h in the ROM. Write 0x55h to address 0x2aaah in the ROM. Write 0xa0h to address 0x5555h in the ROM. Write byte-data to desired address in the ROM.
Memory chips are identified by first entering the software-id mode: Write 0xaah to address 0x5555h in the ROM. Write 0x55h to address 0x2aaah in the ROM. Write 0x90h to address 0x5555h in the ROM.
Now the 'manufacturer ID' and the 'device ID' bytes can be read from addresses 0 and 1 in the ROM, respectively.
After reading the IDs, exit software-id mode thusly: Write 0xaah to address 0x5555h in the ROM. Write 0x55h to address 0x2aaah in the ROM. Write 0xf0h to address 0x5555h in the ROM.
And so on. Grab a datasheet for the flash ROM chip you are working with, this will most likely be documented there too.
//Peter
On Thursday, May 8, 2003, at 10:56 AM, Peter Stuge wrote:
To clarify this a bit;
Most flash ROM chips are identified, erased and programmed according to a standard set by JEDEC.
E.g. for byte-program:
Write 0xaah to address 0x5555h in the ROM. Write 0x55h to address 0x2aaah in the ROM. Write 0xa0h to address 0x5555h in the ROM. Write byte-data to desired address in the ROM.
Memory chips are identified by first entering the software-id mode: Write 0xaah to address 0x5555h in the ROM. Write 0x55h to address 0x2aaah in the ROM. Write 0x90h to address 0x5555h in the ROM.
Now the 'manufacturer ID' and the 'device ID' bytes can be read from addresses 0 and 1 in the ROM, respectively.
After reading the IDs, exit software-id mode thusly: Write 0xaah to address 0x5555h in the ROM. Write 0x55h to address 0x2aaah in the ROM. Write 0xf0h to address 0x5555h in the ROM.
And so on. Grab a datasheet for the flash ROM chip you are working with, this will most likely be documented there too.
I have these, the problem is in detecting the flash in the first place, these sequences of commands don't return what they should. Ron is telling me this is because the write enable bit isn't set. So I now have the docks for the SiS5595 that I didn't know I had (doesn't show in lspci). So what I need to know is how to get access to the registers in the SiS 5595 that set the write enable so that we can detect it properly... and then all the JEDEC stuff would work.
On Thu, May 08, 2003 at 11:30:19AM -0600, Nathanael Noblet wrote:
On Thursday, May 8, 2003, at 10:56 AM, Peter Stuge wrote:
Memory chips are identified by first entering the software-id mode: Write 0xaah to address 0x5555h in the ROM. Write 0x55h to address 0x2aaah in the ROM. Write 0x90h to address 0x5555h in the ROM.
Now the 'manufacturer ID' and the 'device ID' bytes can be read from addresses 0 and 1 in the ROM, respectively.
After reading the IDs, exit software-id mode thusly: Write 0xaah to address 0x5555h in the ROM. Write 0x55h to address 0x2aaah in the ROM. Write 0xf0h to address 0x5555h in the ROM.
I have these, the problem is in detecting the flash in the first place, these sequences of commands don't return what they should. Ron is telling me this is because the write enable bit isn't set.
Exactly, three writes to the chip are required before the ID can be read. Without write enable signals flying the right way, no ID will be found. (Reading the ID is how the flash is "detected".)
So I now have the docks for the SiS5595 that I didn't know I had (doesn't show in lspci). So what I need to know is how to get access to the registers in the SiS 5595 that set the write enable so that we can detect it properly... and then all the JEDEC stuff would work.
Yep, I saw that you've got this down now. Excellent! :)
//Peter
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Nathanael Noblet -
Peter Stuge -
ron minnich